diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-06-27 14:26:07 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-07-01 17:52:17 +0000 |
| commit | a171399796289ad691c599cc9273cd00612a3873 (patch) | |
| tree | d1bba07af6abc7a7de0cd209752f4056b45fc8a8 | |
| parent | 804279cdb752ef48fa2cd0f263522c7d6c53b20c (diff) | |
| download | chrome-ec-a171399796289ad691c599cc9273cd00612a3873.tar.gz | |
chip/npcx/system_chip.h: Format with clang-format
BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: I8fbda8d15740fdc0a0656e83fb162d85db878911
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729443
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
| -rw-r--r-- | chip/npcx/system_chip.h | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h index 2314f1458a..6da21b3e53 100644 --- a/chip/npcx/system_chip.h +++ b/chip/npcx/system_chip.h @@ -9,34 +9,34 @@ #define __CROS_EC_SYSTEM_CHIP_H /* Flags for BBRM_DATA_INDEX_WAKE */ -#define HIBERNATE_WAKE_MTC BIT(0) /* MTC alarm */ -#define HIBERNATE_WAKE_PIN BIT(1) /* Wake pin */ -#define HIBERNATE_WAKE_LCT BIT(2) /* LCT alarm */ +#define HIBERNATE_WAKE_MTC BIT(0) /* MTC alarm */ +#define HIBERNATE_WAKE_PIN BIT(1) /* Wake pin */ +#define HIBERNATE_WAKE_LCT BIT(2) /* LCT alarm */ /* * Indicate that EC enters hibernation via PSL. When EC wakes up from * hibernation and this flag is set, it will check the related status bit to * know the actual wake up source. (From LCT or physical wakeup pins) */ -#define HIBERNATE_WAKE_PSL BIT(3) +#define HIBERNATE_WAKE_PSL BIT(3) /* Indices for battery-backed ram (BBRAM) data position */ enum bbram_data_index { - BBRM_DATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */ + BBRM_DATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */ BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4, /* Saved reset flags */ - BBRM_DATA_INDEX_WAKE = 8, /* Wake reasons for hibernate */ - BBRM_DATA_INDEX_PD0 = 12, /* USB-PD saved port0 state */ - BBRM_DATA_INDEX_PD1 = 13, /* USB-PD saved port1 state */ - BBRM_DATA_INDEX_TRY_SLOT = 14, /* Vboot EC try slot */ - BBRM_DATA_INDEX_PD2 = 15, /* USB-PD saved port2 state */ + BBRM_DATA_INDEX_WAKE = 8, /* Wake reasons for hibernate */ + BBRM_DATA_INDEX_PD0 = 12, /* USB-PD saved port0 state */ + BBRM_DATA_INDEX_PD1 = 13, /* USB-PD saved port1 state */ + BBRM_DATA_INDEX_TRY_SLOT = 14, /* Vboot EC try slot */ + BBRM_DATA_INDEX_PD2 = 15, /* USB-PD saved port2 state */ /* Index 16-31 available for future use */ - BBRM_DATA_INDEX_RAMLOG = 32, /* RAM log for Booter */ - BBRM_DATA_INDEX_PANIC_FLAGS = 35, /* Flag to indicate validity of - * panic data starting at index - * 36. - */ - BBRM_DATA_INDEX_PANIC_BKUP = 36, /* Panic data (index 35-63)*/ - BBRM_DATA_INDEX_LCT_TIME = 64, /* The start time of LCT(4 bytes) - */ + BBRM_DATA_INDEX_RAMLOG = 32, /* RAM log for Booter */ + BBRM_DATA_INDEX_PANIC_FLAGS = 35, /* Flag to indicate validity of + * panic data starting at index + * 36. + */ + BBRM_DATA_INDEX_PANIC_BKUP = 36, /* Panic data (index 35-63)*/ + BBRM_DATA_INDEX_LCT_TIME = 64, /* The start time of LCT(4 bytes) + */ }; enum psl_pin_t { @@ -69,7 +69,7 @@ void system_check_bbram_on_reset(void); #if defined(CHIP_FAMILY_NPCX5) /* Bypass for GMDA issue of ROM api utilities only on npcx5 series */ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, - uint32_t size, uint32_t exeAddr); + uint32_t size, uint32_t exeAddr); /* Begin address for hibernate utility; defined in linker script */ extern unsigned int __flash_lpfw_start; |