nissa: Add initial nereid configuration

Add initial Nereid files and configuration.
Quite a lot of configuration disabled because of the
broken host interface.

GPIO DTS generated by:

./pinmap --chip=IT81302 --output=nereid_generated.dts /tmp/nissa.csv

BUG=b:201000844
TEST=zmake configure -b nereid
BRANCH=none

Signed-off-by: Andrew McRae <amcrae@google.com>
Change-Id: I1f6b2c8f5199d3b2242e41de133b12260eced836
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3353049
Reviewed-by: Peter Marheine <pmarheine@chromium.org>

8 files changed, 677 insertions, 8 deletions

diff --git a/zephyr/boards/riscv/it8xxx2/it8xxx2.dts b/zephyr/boards/riscv/it8xxx2/it8xxx2.dts
index 07fc3eaac3..7673872dfc 100644
--- a/zephyr/boards/riscv/it8xxx2/it8xxx2.dts
+++ b/zephyr/boards/riscv/it8xxx2/it8xxx2.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio_defines.h>
 #include <cros/ite/it8xxx2.dtsi>
 #include <it8xxx2.dtsi>
 
diff --git a/zephyr/projects/nissa/BUILD.py b/zephyr/projects/nissa/BUILD.py
index c1bda5bb97..0af2f6171e 100644
--- a/zephyr/projects/nissa/BUILD.py
+++ b/zephyr/projects/nissa/BUILD.py
@@ -32,3 +32,13 @@ register_nissa_project(
     ],
     extra_kconfig_files=[here / "prj_nivviks.conf"],
 )
+
+register_nissa_project(
+    project_name="nereid",
+    chip="it8xxx2",
+    extra_dts_overlays=[
+        here / "nereid_generated.dts",
+        here / "nereid_overlay.dts",
+    ],
+    extra_kconfig_files=[here / "prj_nereid.conf"],
+)
diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt
index 7acb42b1bb..c8ab00f123 100644
--- a/zephyr/projects/nissa/CMakeLists.txt
+++ b/zephyr/projects/nissa/CMakeLists.txt
@@ -11,3 +11,6 @@ zephyr_include_directories(include)
 if(DEFINED CONFIG_BOARD_NIVVIKS)
 	project(nivviks)
 endif()
+if(DEFINED CONFIG_BOARD_NEREID)
+	project(nereid)
+endif()
diff --git a/zephyr/projects/nissa/Kconfig b/zephyr/projects/nissa/Kconfig
index 6f6176e0dc..3f8196bf8a 100644
--- a/zephyr/projects/nissa/Kconfig
+++ b/zephyr/projects/nissa/Kconfig
@@ -8,4 +8,10 @@ config BOARD_NIVVIKS
 	  Build Google Nivviks reference board. Nivviks has Intel ADL-N SoC
 	  with NPCX993FA0BX EC.
 
+config BOARD_NEREID
+	bool "Google Nereid Board"
+	help
+	  Build Google Nereid reference board. Nereid has Intel ADL-N SoC
+	  with IT81302 EC.
+
 source "Kconfig.zephyr"
diff --git a/zephyr/projects/nissa/include/gpio_map.h b/zephyr/projects/nissa/include/gpio_map.h
index d344e88c9b..bc79e11f17 100644
--- a/zephyr/projects/nissa/include/gpio_map.h
+++ b/zephyr/projects/nissa/include/gpio_map.h
@@ -25,6 +25,7 @@
  *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
  */
 /* Helper macros for generating CROS_EC_GPIO_INTERRUPTS */
+
 #ifdef CONFIG_PLATFORM_EC_POWERSEQ
 #define POWER_SIGNAL_INT(gpio, edge) \
 	GPIO_INT(gpio, edge, power_signal_interrupt)
@@ -35,14 +36,39 @@
 #define AP_PROCHOT_INT(gpio, edge)
 #endif
 
+#ifdef CONFIG_PLATFORM_EC_POWER_BUTTON
+	#define PWRBTN_INT()        GPIO_INT(GPIO_POWER_BUTTON_L,              \
+					     GPIO_INT_EDGE_BOTH,               \
+					     power_button_interrupt)
+#else
+	#define PWRBTN_INT()
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_LID_SWITCH
+	#define LID_INT()       GPIO_INT(GPIO_LID_OPEN, \
+				GPIO_INT_EDGE_BOTH,     \
+				lid_interrupt)
+#else
+	#define LID_INT()
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_VOLUME_BUTTONS
+	#define VOLBTN_INT(pin)     GPIO_INT(pin,                             \
+					     GPIO_INT_EDGE_BOTH,              \
+					     button_interrupt)
+#else
+	#define VOLBTN_INT(pin)
+#endif
+
 
-#define EC_CROS_GPIO_INTERRUPTS                                           \
-	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)        \
-	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                 \
-		 power_button_interrupt)                                  \
-	POWER_SIGNAL_INT(GPIO_SLP_SUS_L, GPIO_INT_EDGE_BOTH)              \
-	POWER_SIGNAL_INT(GPIO_PG_EC_DSW_PWROK, GPIO_INT_EDGE_BOTH)        \
-	POWER_SIGNAL_INT(GPIO_PG_EC_RSMRST_ODL, GPIO_INT_EDGE_BOTH)       \
-	POWER_SIGNAL_INT(GPIO_PG_EC_ALL_SYS_PWRGD, GPIO_INT_EDGE_BOTH)    \
+#define EC_CROS_GPIO_INTERRUPTS                                         \
+	LID_INT()							\
+	PWRBTN_INT()							\
+	VOLBTN_INT(GPIO_VOLUME_DOWN_L)					\
+	VOLBTN_INT(GPIO_VOLUME_UP_L)					\
+	POWER_SIGNAL_INT(GPIO_SLP_SUS_L, GPIO_INT_EDGE_BOTH)            \
+	POWER_SIGNAL_INT(GPIO_PG_EC_DSW_PWROK, GPIO_INT_EDGE_BOTH)      \
+	POWER_SIGNAL_INT(GPIO_PG_EC_RSMRST_ODL, GPIO_INT_EDGE_BOTH)     \
+	POWER_SIGNAL_INT(GPIO_PG_EC_ALL_SYS_PWRGD, GPIO_INT_EDGE_BOTH)  \
 	AP_PROCHOT_INT(GPIO_EC_PROCHOT_ODL, GPIO_INT_EDGE_BOTH)
 #endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/nissa/nereid_generated.dts b/zephyr/projects/nissa/nereid_generated.dts
new file mode 100644
index 0000000000..0f4a0f4ee2
--- /dev/null
+++ b/zephyr/projects/nissa/nereid_generated.dts
@@ -0,0 +1,418 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			label = "EC_VSENSE_PP3300_S5";
+			enum-name = "ADC_PP3300_S5";
+			channel = <0>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			label = "TEMP_SENSOR_1";
+			enum-name = "ADC_TEMP_SENSOR_1";
+			channel = <2>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			label = "TEMP_SENSOR_2";
+			enum-name = "ADC_TEMP_SENSOR_2";
+			channel = <3>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			label = "TEMP_SENSOR_3";
+			enum-name = "ADC_TEMP_SENSOR_3";
+			channel = <13>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acc_int_l: acc_int_l {
+			#gpio-cells = <0>;
+			gpios = <&gpioc 0 GPIO_INPUT>;
+			label = "ACC_INT_L";
+			enum-name = "GPIO_LID_ACCEL_INT_L";
+		};
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			#gpio-cells = <0>;
+			gpios = <&gpiob 7 GPIO_INPUT>;
+			label = "ALL_SYS_PWRGD";
+			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpioh 5 GPIO_INPUT>;
+			label = "CCD_MODE_ODL";
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			#gpio-cells = <0>;
+			gpios = <&gpiog 1 GPIO_INPUT>;
+			label = "CPU_C10_GATE_L";
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpioi 4 GPIO_INPUT>;
+			label = "EC_BATTERY_PRES_ODL";
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			#gpio-cells = <0>;
+			gpios = <&gpioj 5 GPIO_OUTPUT>;
+			label = "EC_CBI_WP";
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			#gpio-cells = <0>;
+			gpios = <&gpiok 4 GPIO_ODR_HIGH>;
+			label = "EC_EDP_BL_EN_OD";
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			#gpio-cells = <0>;
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+			label = "EC_ENTERING_RW";
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			#gpio-cells = <0>;
+			gpios = <&gpioh 1 GPIO_INPUT>;
+			label = "EC_GSC_PACKET_MODE";
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpioi 1 GPIO_INPUT>;
+			label = "EC_PROCHOT_ODL";
+			enum-name = "GPIO_CPU_PROCHOT";
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			#gpio-cells = <0>;
+			gpios = <&gpiol 7 GPIO_OUTPUT>;
+			label = "EC_SOC_DSW_PWROK";
+			enum-name = "GPIO_PG_EC_DSW_PWROK";
+		};
+		gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd {
+			#gpio-cells = <0>;
+			gpios = <&gpiok 7 GPIO_OUTPUT>;
+			label = "EC_SOC_HDMI_HPD";
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpiob 2 GPIO_ODR_LOW>;
+			label = "EC_SOC_INT_ODL";
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			#gpio-cells = <0>;
+			gpios = <&gpiod 6 GPIO_ODR_HIGH>;
+			label = "EC_SOC_PCH_PWROK_OD";
+			enum-name = "GPIO_PCH_PWROK";
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpiob 6 GPIO_ODR_LOW>;
+			label = "EC_SOC_PWR_BTN_ODL";
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			#gpio-cells = <0>;
+			gpios = <&gpioh 0 GPIO_OUTPUT>;
+			label = "EC_SOC_RSMRST_L";
+			enum-name = "GPIO_PCH_RSMRST_L";
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			#gpio-cells = <0>;
+			gpios = <&gpiok 2 GPIO_OUTPUT>;
+			label = "EC_SOC_RTCRST";
+			enum-name = "GPIO_PCH_RTCRST";
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			#gpio-cells = <0>;
+			gpios = <&gpiof 2 GPIO_OUTPUT>;
+			label = "EC_SOC_SYS_PWROK";
+			enum-name = "GPIO_PCH_SYS_PWROK";
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			#gpio-cells = <0>;
+			gpios = <&gpioe 5 GPIO_ODR_HIGH>;
+			label = "EC_SOC_VCCST_PWRGD_OD";
+			enum-name = "GPIO_VCCST_PWRGD_OD";
+		};
+		gpio_ec_soc_wake_odl: ec_soc_wake_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpiod 5 GPIO_ODR_LOW>;
+			label = "EC_SOC_WAKE_ODL";
+			enum-name = "GPIO_EC_PCH_WAKE_ODL";
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpioa 6 GPIO_INPUT>;
+			label = "EC_WP_ODL";
+			enum-name = "GPIO_WP_L";
+		};
+		gpio_en_kb_bl: en_kb_bl {
+			#gpio-cells = <0>;
+			gpios = <&gpioj 3 GPIO_OUTPUT>;
+			label = "EN_KB_BL";
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			#gpio-cells = <0>;
+			gpios = <&gpioc 5 GPIO_OUTPUT>;
+			label = "EN_PP3300_S5";
+			enum-name = "GPIO_EN_PP3300_A";
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			#gpio-cells = <0>;
+			gpios = <&gpiob 5 GPIO_OUTPUT>;
+			label = "EN_PP5000_PEN_X";
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			#gpio-cells = <0>;
+			gpios = <&gpiok 5 GPIO_OUTPUT>;
+			label = "EN_PP5000_S5";
+			enum-name = "GPIO_EN_PP5000";
+		};
+		gpio_en_slp_z: en_slp_z {
+			#gpio-cells = <0>;
+			gpios = <&gpiok 3 GPIO_OUTPUT>;
+			label = "EN_SLP_Z";
+			enum-name = "GPIO_EN_SLP_Z";
+		};
+		gpio_en_sub_usb_a1_vbus: en_sub_usb_a1_vbus {
+			#gpio-cells = <0>;
+			gpios = <&gpiof 0 GPIO_OUTPUT>;
+			label = "EN_SUB_USB_A1_VBUS";
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			#gpio-cells = <0>;
+			gpios = <&gpiol 6 GPIO_OUTPUT>;
+			label = "EN_USB_A0_VBUS";
+			enum-name = "GPIO_EN_USB_A_5V";
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpioe 2 GPIO_INPUT>;
+			label = "GSC_EC_PWR_BTN_ODL";
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_hdmi_sel: hdmi_sel {
+			#gpio-cells = <0>;
+			gpios = <&gpioc 6 GPIO_OUTPUT>;
+			label = "HDMI_SEL";
+		};
+		gpio_imu_int_l: imu_int_l {
+			#gpio-cells = <0>;
+			gpios = <&gpioj 0 GPIO_INPUT>;
+			label = "IMU_INT_L";
+			enum-name = "GPIO_EC_IMU_INT_L";
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			#gpio-cells = <0>;
+			gpios = <&gpioj 4 GPIO_INPUT>;
+			label = "IMVP91_VRRDY_OD";
+			enum-name = "GPIO_IMVP9_VRRDY_OD";
+		};
+		gpio_lid_open: lid_open {
+			#gpio-cells = <0>;
+			gpios = <&gpiof 3 GPIO_INPUT>;
+			label = "LID_OPEN";
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpioj 1 GPIO_INPUT>;
+			label = "PEN_DETECT_ODL";
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			#gpio-cells = <0>;
+			gpios = <&gpiod 3 GPIO_INPUT>;
+			label = "PG_PP1050_MEM_S3_OD";
+		};
+		gpio_pg_pp1050_proc: pg_pp1050_proc {
+			#gpio-cells = <0>;
+			gpios = <&gpiol 1 GPIO_INPUT>;
+			label = "PG_PP1050_PROC";
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			#gpio-cells = <0>;
+			gpios = <&gpioe 3 GPIO_INPUT>;
+			label = "PG_PP5000_S5_OD";
+			enum-name = "GPIO_PG_PP5000_A_ODL";
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			#gpio-cells = <0>;
+			gpios = <&gpioe 1 GPIO_INPUT>;
+			label = "RSMRST_PWRGD_L";
+			enum-name = "GPIO_PG_EC_RSMRST_ODL";
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			#gpio-cells = <0>;
+			gpios = <&gpioe 4 GPIO_INPUT>;
+			label = "SLP_S0_L";
+			enum-name = "GPIO_PCH_SLP_S0_L";
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			#gpio-cells = <0>;
+			gpios = <&gpioh 3 GPIO_INPUT>;
+			label = "SLP_S3_L";
+			enum-name = "GPIO_PCH_SLP_S3_L";
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			#gpio-cells = <0>;
+			gpios = <&gpioi 5 GPIO_INPUT>;
+			label = "SLP_S4_L";
+			enum-name = "GPIO_PCH_SLP_S4_L";
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			#gpio-cells = <0>;
+			gpios = <&gpiog 2 GPIO_INPUT>;
+			label = "SLP_SUS_L";
+			enum-name = "GPIO_SLP_SUS_L";
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			#gpio-cells = <0>;
+			gpios = <&gpiof 1 GPIO_OUTPUT>;
+			label = "SUB_USB_A1_ILIMIT_SDP";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpiod 1 GPIO_ODR_LOW>;
+			label = "SYS_RST_ODL";
+			enum-name = "GPIO_SYS_RESET_L";
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			#gpio-cells = <0>;
+			gpios = <&gpioa 7 GPIO_INPUT>;
+			label = "TABLET_MODE_L";
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			#gpio-cells = <0>;
+			gpios = <&gpiol 5 GPIO_OUTPUT>;
+			label = "USB_A0_ILIMIT_SDP";
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpiok 0 GPIO_INPUT>;
+			label = "USB_C0_INT_ODL";
+			enum-name = "GPIO_USB_C0_PD_INT_ODL";
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			#gpio-cells = <0>;
+			gpios = <&gpiod 0 GPIO_INPUT>;
+			label = "VCCIN_AUX_VID0";
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			#gpio-cells = <0>;
+			gpios = <&gpiok 1 GPIO_INPUT>;
+			label = "VCCIN_AUX_VID1";
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpioi 6 GPIO_INPUT>;
+			label = "VOLDN_BTN_ODL";
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpioi 7 GPIO_INPUT>;
+			label = "VOLUP_BTN_ODL";
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c1>;
+			enum-name = "I2C_PORT_BATTERY";
+		};
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0>;
+			enum-name = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c2>;
+			enum-name = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c4>;
+			enum-name = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c5>;
+			enum-name = "I2C_PORT_USB_C0_TCPC";
+		};
+	};
+
+	named-pwms {
+		compatible = "named-pwms";
+
+		pwm_pwm_kb_bl: pwm_kb_bl {
+			pwms = <&pwm0 0 0>;
+			label = "PWM_KB_BL";
+		};
+		pwm_pwm_led_1_odl: pwm_led_1_odl {
+			pwms = <&pwm1 1 1>;
+			label = "PWM_LED_1_ODL";
+		};
+		pwm_pwm_led_2_odl: pwm_led_2_odl {
+			pwms = <&pwm2 2 1>;
+			label = "PWM_LED_2_ODL";
+		};
+		pwm_pwm_led_3_odl: pwm_led_3_odl {
+			pwms = <&pwm3 3 1>;
+			label = "PWM_LED_3_ODL";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&pwm3 {
+	status = "okay";
+};
diff --git a/zephyr/projects/nissa/nereid_overlay.dts b/zephyr/projects/nissa/nereid_overlay.dts
new file mode 100644
index 0000000000..5b591bdb0f
--- /dev/null
+++ b/zephyr/projects/nissa/nereid_overlay.dts
@@ -0,0 +1,128 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-pins = <
+			&gpio_gsc_ec_pwr_btn_odl
+			&gpio_lid_open
+		>;
+	};
+
+	named-temp-sensors {
+		memory {
+			compatible = "cros-ec,temp-sensor-thermistor";
+			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+			label = "DDR and SOC";
+			enum-name = "TEMP_SENSOR_1";
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			adc = <&adc_temp_sensor_1>;
+		};
+		charger {
+			compatible = "cros-ec,temp-sensor-thermistor";
+			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+			label = "Charger";
+			enum-name = "TEMP_SENSOR_CHARGER";
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			adc = <&adc_temp_sensor_2>;
+		};
+		ambient {
+			compatible = "cros-ec,temp-sensor-thermistor";
+			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+			label = "Ambiient";
+			enum-name = "TEMP_SENSOR_AMB";
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			adc = <&adc_temp_sensor_3>;
+		};
+	};
+
+	/*
+	 * Alias kblist to correct node.
+	 */
+	named-pwms {
+		compatible = "named-pwms";
+
+		kblight: pwm_kb_bl {
+		};
+	};
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+/* Set bus speeds for I2C */
+&i2c0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c1 {
+	label = "I2C_BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&i2c2 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c4 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c5 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+/* PWM config */
+&pwm0 {
+	prescaler-cx = <PWM_PRESCALER_C4>;
+};
+
+&pwm1 {
+	prescaler-cx = <PWM_PRESCALER_C4>;
+};
+
+&pwm2 {
+	prescaler-cx = <PWM_PRESCALER_C4>;
+};
+
+&pwm3 {
+	prescaler-cx = <PWM_PRESCALER_C4>;
+};
+
+&pwm_pwm_kb_bl {
+	frequency = <10000>;
+};
+
+&pwm_pwm_led_1_odl {
+	frequency = <324>;
+};
+
+&pwm_pwm_led_2_odl {
+	frequency = <324>;
+};
+
+&pwm_pwm_led_3_odl {
+	frequency = <324>;
+};
diff --git a/zephyr/projects/nissa/prj_nereid.conf b/zephyr/projects/nissa/prj_nereid.conf
new file mode 100644
index 0000000000..d3294b9853
--- /dev/null
+++ b/zephyr/projects/nissa/prj_nereid.conf
@@ -0,0 +1,77 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_SHIMMED_TASKS=y
+
+# Variant config
+CONFIG_BOARD_NEREID=y
+
+# Bringup options
+CONFIG_KERNEL_SHELL=y
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+CONFIG_PLATFORM_EC_HOSTCMD=n
+
+CONFIG_PLATFORM_EC_POWER_BUTTON=n
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_LTO=y
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+CONFIG_PLATFORM_EC_I2C=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
+
+# SoC configuration
+CONFIG_AP=n
+#CONFIG_AP_X86_INTEL_ADL=y
+
+# Host command
+#CONFIG_PLATFORM_EC_HOSTCMD=y
+#CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+#CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+#CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y
+#CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y
+
+# Temperature sensors - disabled until host interface is available
+#CONFIG_PLATFORM_EC_TEMP_SENSOR=y
+#CONFIG_PLATFORM_EC_THERMISTOR=y
+
+# PWM
+CONFIG_PWM=y
+CONFIG_PWM_SHELL=y
+CONFIG_PLATFORM_EC_PWM=y
+#CONFIG_PLATFORM_EC_PWM_KBLIGHT=y
+
+# Keyboard - disabled until host interface is available
+CONFIG_CROS_KB_RAW_ITE=n
+CONFIG_PLATFORM_EC_KEYBOARD=n
+#CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y
+#CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+#CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+#CONFIG_PLATFORM_EC_CMD_BUTTON=y
+
+# MKBP event mask
+#CONFIG_PLATFORM_EC_MKBP_EVENT=y
+#CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+#CONFIG_PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK=y
+#CONFIG_PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK=y
+#CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
+
+# TODO(b/188605676): bring these features up
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n
+CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n
+
+# Power Sequencing
+# TODO(b/203446068): Implement ADL-N power sequence.
+#CONFIG_PLATFORM_EC_POWERSEQ=y
+#CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+#CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540=y
+#CONFIG_PLATFORM_EC_POWERSEQ_RTC_RESET=n
+#CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
+#CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+# Treat 2nd reset from H1 as Power-On
+CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y
+CONFIG_PLATFORM_EC_THROTTLE_AP=y