zephyr/emul/retimer/anx7483: Add function to validate tuning settings

Board tests may want to have a basic check to ensure that tunings are
getting set, while the actual full testing remains in the ANX7483
emulator tests. Add `anx7483_emul_validate_tuning` function to
facilitate this.

BRANCH=none
BUG=b:247151116
TEST=Ran tests

Change-Id: I88ce43b079db98d16aedf561a463df0046c4460b
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4354875
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>

5 files changed, 228 insertions, 483 deletions

diff --git a/driver/retimer/anx7483.c b/driver/retimer/anx7483.c
index 3cb840dfa5..4b07848b9e 100644
--- a/driver/retimer/anx7483.c
+++ b/driver/retimer/anx7483.c
@@ -25,13 +25,7 @@
 #define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 #define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-/* Tuning defaults */
-struct anx7483_tuning_set {
-	uint8_t addr;
-	uint8_t value;
-};
-
-const static struct anx7483_tuning_set anx7483_usb_enabled[] = {
+const test_export_static struct anx7483_tuning_set anx7483_usb_enabled[] = {
 	{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
 	{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
 	{ ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
@@ -68,7 +62,7 @@ const static struct anx7483_tuning_set anx7483_usb_enabled[] = {
 	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
 };
 
-static struct anx7483_tuning_set anx7483_dp_enabled[] = {
+const test_export_static struct anx7483_tuning_set anx7483_dp_enabled[] = {
 	{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
 
 	{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
@@ -105,7 +99,7 @@ static struct anx7483_tuning_set anx7483_dp_enabled[] = {
 	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
 };
 
-static struct anx7483_tuning_set anx7483_dock_noflip[] = {
+const test_export_static struct anx7483_tuning_set anx7483_dock_noflip[] = {
 	{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
 
 	{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
@@ -143,7 +137,7 @@ static struct anx7483_tuning_set anx7483_dock_noflip[] = {
 	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
 };
 
-static struct anx7483_tuning_set anx7483_dock_flip[] = {
+const test_export_static struct anx7483_tuning_set anx7483_dock_flip[] = {
 	{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
 
 	{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
@@ -181,6 +175,11 @@ static struct anx7483_tuning_set anx7483_dock_flip[] = {
 	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
 };
 
+const size_t anx7483_usb_enabled_count = ARRAY_SIZE(anx7483_usb_enabled);
+const size_t anx7483_dp_enabled_count = ARRAY_SIZE(anx7483_dp_enabled);
+const size_t anx7483_dock_noflip_count = ARRAY_SIZE(anx7483_dock_noflip);
+const size_t anx7483_dock_flip_count = ARRAY_SIZE(anx7483_dock_flip);
+
 test_export_static int anx7483_read(const struct usb_mux *me, uint8_t reg,
 				    int *val)
 {
diff --git a/driver/retimer/anx7483.h b/driver/retimer/anx7483.h
index 3120e3c707..a478f5abf6 100644
--- a/driver/retimer/anx7483.h
+++ b/driver/retimer/anx7483.h
@@ -8,6 +8,14 @@
 #ifndef __CROS_EC_USB_RETIMER_ANX7483_H
 #define __CROS_EC_USB_RETIMER_ANX7483_H
 
+#include "common.h"
+
+/* Tuning defaults */
+struct anx7483_tuning_set {
+	uint8_t addr;
+	uint8_t value;
+};
+
 /*
  * LFPS_TIMER register
  *
diff --git a/zephyr/emul/retimer/emul_anx7483.c b/zephyr/emul/retimer/emul_anx7483.c
index 507eaff2ce..13c6e39d43 100644
--- a/zephyr/emul/retimer/emul_anx7483.c
+++ b/zephyr/emul/retimer/emul_anx7483.c
@@ -337,6 +337,25 @@ void anx7483_emul_reset(const struct emul *emul)
 				     anx7483->regs[i].def);
 }
 
+int anx7483_emul_validate_tuning(const struct emul *emul,
+				 const struct anx7483_tuning_set *tuning,
+				 size_t tuning_count)
+{
+	uint8_t val;
+	int rv;
+
+	for (size_t i = 0; i < tuning_count; i++) {
+		rv = anx7483_emul_get_reg(emul, tuning[i].addr, &val);
+		if (rv)
+			return rv;
+
+		if (val != tuning[i].value)
+			return 1;
+	}
+
+	return 0;
+}
+
 static int anx7483_emul_init(const struct emul *emul,
 			     const struct device *parent)
 {
diff --git a/zephyr/include/emul/retimer/emul_anx7483.h b/zephyr/include/emul/retimer/emul_anx7483.h
index 2673bebf63..f2b7fe32d4 100644
--- a/zephyr/include/emul/retimer/emul_anx7483.h
+++ b/zephyr/include/emul/retimer/emul_anx7483.h
@@ -129,4 +129,8 @@ int anx7483_emul_get_eq(const struct emul *emul, enum anx7483_tune_pin pin,
 
 void anx7483_emul_reset(const struct emul *emul);
 
+int anx7483_emul_validate_tuning(const struct emul *emul,
+				 const struct anx7483_tuning_set *tuning,
+				 size_t tuning_count);
+
 #endif /* __EMUL_ANX7483_H */
diff --git a/zephyr/test/drivers/usbc_retimer/src/anx7483.c b/zephyr/test/drivers/usbc_retimer/src/anx7483.c
index f3f592b480..1d0d034c14 100644
--- a/zephyr/test/drivers/usbc_retimer/src/anx7483.c
+++ b/zephyr/test/drivers/usbc_retimer/src/anx7483.c
@@ -22,6 +22,16 @@ int anx7483_get(const struct usb_mux *me, mux_state_t *mux_state);
 int anx7483_read(const struct usb_mux *me, uint8_t reg, int *val);
 int anx7483_write(const struct usb_mux *me, uint8_t reg, uint8_t val);
 
+extern const struct anx7483_tuning_set anx7483_usb_enabled[];
+extern const struct anx7483_tuning_set anx7483_dp_enabled[];
+extern const struct anx7483_tuning_set anx7483_dock_noflip[];
+extern const struct anx7483_tuning_set anx7483_dock_flip[];
+
+extern const size_t anx7483_usb_enabled_count;
+extern const size_t anx7483_dp_enabled_count;
+extern const size_t anx7483_dock_noflip_count;
+extern const size_t anx7483_dock_flip_count;
+
 static struct usb_mux mux = {
 	.i2c_port = I2C_PORT_NODELABEL(i2c3),
 	.i2c_addr_flags = 0x3e,
@@ -942,526 +952,231 @@ ZTEST(anx7483, test_emul_update_reserved)
 
 /*
  * Tests that the ANX7483 driver correctly configures the default tuning for
- * USB. The register values should match those in the anx7483_usb_enabled struct
- * within the driver.
+ * USB.
  */
 ZTEST(anx7483, test_tuning_usb)
 {
+	/*
+	 * Vendor defined tuning settings, these should match those in the
+	 * anx7483_usb_enabled struct within the driver.
+	 */
+	const struct anx7483_tuning_set usb_enabled[] = {
+		{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+		{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+		{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+		{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+		{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+		{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+
+		{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+		{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+		{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+		{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+		{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+		{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+
+		{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	};
 	int rv;
-	uint8_t val;
 
 	rv = anx7483_set_default_tuning(&mux, USB_PD_MUX_USB_ENABLED);
 	zexpect_ok(rv);
 
-	/* CFG0 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val);
+	zassert_equal(ARRAY_SIZE(usb_enabled), anx7483_usb_enabled_count);
+	rv = anx7483_emul_validate_tuning(ANX7483_EMUL, usb_enabled,
+					  ARRAY_SIZE(usb_enabled));
 	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	/* CFG1 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	/* CFG2 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	/* CFG3 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_OUT);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_OUT);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_OUT);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_OUT);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
-
-	/* CFG4 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
 }
 
 /*
  * Tests that the ANX7483 driver correctly configures the default tuning for
- * DisplayPort. The register values should match those in the anx7483_dp_enabled
- * struct within the driver.
+ * DisplayPort.
  */
 ZTEST(anx7483, test_tuning_dp)
 {
+	/*
+	 * Vendor defined tuning settings, these should match those in the
+	 * anx7483_dp_enabled struct within the driver.
+	 */
+	const struct anx7483_tuning_set dp_enabled[] = {
+		{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
+
+		{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+		{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+		{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+		{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+		{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	};
 	int rv;
-	uint8_t val;
 
 	rv = anx7483_set_default_tuning(&mux, USB_PD_MUX_DP_ENABLED);
 	zexpect_ok(rv);
 
-	/* CFG0 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	/* CFG1 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	/* CFG2 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	/* CFG3 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	/* CFG4 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG4_REG, &val);
+	zassert_equal(ARRAY_SIZE(dp_enabled), anx7483_dp_enabled_count);
+	rv = anx7483_emul_validate_tuning(ANX7483_EMUL, dp_enabled,
+					  ARRAY_SIZE(dp_enabled));
 	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
 }
 
 /*
  * Tests that the ANX7483 driver correctly configures the default tuning for
- * dock mode in a non-flipped state. The register values should match those in
- * the anx7483_dock_noflip struct within the driver.
+ * dock mode in a non-flipped state.
  */
 ZTEST(anx7483, test_tuning_dock_noflip)
 {
+	/*
+	 * Vendor defined tuning settings, these should match those in the
+	 * anx7483_dock_noflip struct within the driver.
+	 */
+	const test_export_static struct anx7483_tuning_set dock_noflip[] = {
+		{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
+
+		{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+		{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+		{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+		{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+
+		{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+		{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+		{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	};
 	int rv;
-	uint8_t val;
 
 	rv = anx7483_set_default_tuning(&mux, USB_PD_MUX_DOCK);
 	zexpect_ok(rv);
 
-	/* Corresponds to anx7483_dock_noflip. */
-	/* CFG0 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	/* CFG1 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	/* CFG2 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	/* CFG3 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	/* CFG4 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG4_REG, &val);
+	zassert_equal(ARRAY_SIZE(dock_noflip), anx7483_dock_noflip_count);
+	rv = anx7483_emul_validate_tuning(ANX7483_EMUL, dock_noflip,
+					  ARRAY_SIZE(dock_noflip));
 	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
 }
 
 /*
  * Tests that the ANX7483 driver correctly configures the default tuning for
- * dock mode in a flipped state. The register values should match those in
- * the anx7483_dock_flip struct within the driver.
+ * dock mode in a flipped state.
  */
 ZTEST(anx7483, test_tuning_dock_flip)
 {
+	/*
+	 * Vendor defined tuning settings, these should match those in the
+	 * anx7483_dock_flip struct within the driver.
+	 */
+	const test_export_static struct anx7483_tuning_set dock_flip[] = {
+		{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
+
+		{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+		{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+		{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+		{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+
+		{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+		{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+		{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	};
 	int rv;
-	uint8_t val;
 
 	rv = anx7483_set_default_tuning(
 		&mux, USB_PD_MUX_DOCK | USB_PD_MUX_POLARITY_INVERTED);
 	zexpect_ok(rv);
 
-	/* CFG0 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG0_DEF);
-
-	/* CFG1 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG1_DEF);
-
-	/* CFG2 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG2_DEF);
-
-	/* CFG3 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG3_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
-
-	/* CFG4 */
-	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG4_REG, &val);
-	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
-
-	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG4_REG, &val);
+	zassert_equal(ARRAY_SIZE(dock_flip), anx7483_dock_flip_count);
+	rv = anx7483_emul_validate_tuning(ANX7483_EMUL, dock_flip,
+					  ARRAY_SIZE(dock_flip));
 	zexpect_ok(rv);
-	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
 }