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| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-06-27 14:27:41 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-06-30 18:43:51 +0000 |
| commit | a1df99292c7670cda43f626f06441dc911d8eb2a (patch) | |
| tree | 3bff3ec68d62d5cac2cdc9fe88a8dbb0baaf4c79 | |
| parent | f4ab1cb8447d7cc6b6c16ed0003989b1f53834c1 (diff) | |
| download | chrome-ec-a1df99292c7670cda43f626f06441dc911d8eb2a.tar.gz | |
chip/stm32/config-stm32g41xb.h: Format with clang-format
BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: Icf58ba209e9b20473526c173d37e257732461f46
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729476
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
| -rw-r--r-- | chip/stm32/config-stm32g41xb.h | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h index d6ec8696fb..5a4d403957 100644 --- a/chip/stm32/config-stm32g41xb.h +++ b/chip/stm32/config-stm32g41xb.h @@ -17,12 +17,11 @@ * PSTATE in single bank memories with a write size > 4 bytes. */ -#define CONFIG_FLASH_SIZE_BYTES (128 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (128 * 1024) #define CONFIG_FLASH_WRITE_SIZE 0x0004 #define CONFIG_FLASH_BANK_SIZE (2 * 1024) #define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE - /* Erasing 128K can take up to 2s, need to defer erase. */ #define CONFIG_FLASH_DEFERRED_ERASE @@ -37,11 +36,11 @@ * • 10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased * at 0x2000 5800 address to be accessed by all bus controllers. */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00008000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00008000 #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 3 +#define I2C_PORT_COUNT 3 /* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */ #define DMAC_COUNT 12 @@ -51,13 +50,13 @@ #undef CONFIG_FLASH_PSTATE_BANK /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 101 +#define CONFIG_IRQ_COUNT 101 /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 1024 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 1024 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t #define CONFIG_USB_RAM_ACCESS_SIZE 2 /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 |