nissa/nivviks: configure USB-C

This enables chargers, TCPCs, BC1.2 and muxes all at once because each
is intertwined with the whole of USB-C support.

Board-specific functions are largely taken from lalala's implementation,
since that board also uses dual RAA489000s.

BUG=b:211693800,b:212490923
TEST=builds
BRANCH=none

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Ib84324d29d4435ed1a4dfeb4d48c3a79afda5516
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3354263
Reviewed-by: Andrew McRae <amcrae@google.com>

6 files changed, 400 insertions, 1 deletions

diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt
index c8ab00f123..fae80277f9 100644
--- a/zephyr/projects/nissa/CMakeLists.txt
+++ b/zephyr/projects/nissa/CMakeLists.txt
@@ -10,6 +10,8 @@ zephyr_include_directories(include)
 
 if(DEFINED CONFIG_BOARD_NIVVIKS)
 	project(nivviks)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/charger.c")
 endif()
 if(DEFINED CONFIG_BOARD_NEREID)
 	project(nereid)
diff --git a/zephyr/projects/nissa/include/gpio_map.h b/zephyr/projects/nissa/include/gpio_map.h
index bc79e11f17..661f8d403e 100644
--- a/zephyr/projects/nissa/include/gpio_map.h
+++ b/zephyr/projects/nissa/include/gpio_map.h
@@ -60,6 +60,14 @@
 	#define VOLBTN_INT(pin)
 #endif
 
+#ifdef CONFIG_PLATFORM_EC_USBC
+	#define USBC_INT(pin, port)	GPIO_INT(pin,			      \
+						 GPIO_INT_EDGE_FALLING,	      \
+						 usb_c ## port ## _interrupt)
+#else
+	#define USBC_INT(pin, port)
+#endif
+
 
 #define EC_CROS_GPIO_INTERRUPTS                                         \
 	LID_INT()							\
@@ -70,5 +78,7 @@
 	POWER_SIGNAL_INT(GPIO_PG_EC_DSW_PWROK, GPIO_INT_EDGE_BOTH)      \
 	POWER_SIGNAL_INT(GPIO_PG_EC_RSMRST_ODL, GPIO_INT_EDGE_BOTH)     \
 	POWER_SIGNAL_INT(GPIO_PG_EC_ALL_SYS_PWRGD, GPIO_INT_EDGE_BOTH)  \
-	AP_PROCHOT_INT(GPIO_EC_PROCHOT_ODL, GPIO_INT_EDGE_BOTH)
+	AP_PROCHOT_INT(GPIO_EC_PROCHOT_ODL, GPIO_INT_EDGE_BOTH)		\
+	USBC_INT(GPIO_USB_C0_PD_INT_ODL, 0)				\
+	USBC_INT(GPIO_USB_C1_PD_INT_ODL, 1)
 #endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/nissa/nivviks_overlay.dts b/zephyr/projects/nissa/nivviks_overlay.dts
index a6d4c6f0c7..86fa044c5d 100644
--- a/zephyr/projects/nissa/nivviks_overlay.dts
+++ b/zephyr/projects/nissa/nivviks_overlay.dts
@@ -20,6 +20,20 @@
 		>;
 	};
 
+	named-gpios {
+		/*
+		 * TODO(b:212490923): decide what to do with these sorts of
+		 * signals that have varying function depending on the present
+		 * sub-board.
+		 */
+		gpio_sub_usb_c1_int_odl: sub_usb_c1_int_odl {
+			#gpio-cells = <0>;
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			label = "SUB_USB_C1_INT_ODL";
+			enum-name = "GPIO_USB_C1_PD_INT_ODL";
+		};
+	};
+
 	named-temp-sensors {
 		memory {
 			compatible = "cros-ec,temp-sensor-thermistor";
@@ -58,6 +72,30 @@
 		kblight: pwm_kb_bl {
 		};
 	};
+
+	usbc {
+		port0 {
+			bc12 {
+				compatible = "pericom,pi3usb9201";
+				port = <&i2c_ec_i2c_usb_c0>;
+				/*
+				 * BC1.2 interrupt is shared with TCPC, so
+				 * IRQ is not specified here and handled by
+				 * usb_c0_interrupt.
+				 */
+			};
+		};
+		/*
+		 * TODO(b:211693800): port1 may not be present on some
+		 * sub-boards.
+		 */
+		port1 {
+			bc12 {
+				compatible = "pericom,pi3usb9201";
+				port = <&i2c_ec_i2c_sub_usb_c1>;
+			};
+		};
+	};
 };
 
 &thermistor_3V3_51K1_47K_4050B {
diff --git a/zephyr/projects/nissa/prj_nivviks.conf b/zephyr/projects/nissa/prj_nivviks.conf
index e44f6061ed..7a9513bf50 100644
--- a/zephyr/projects/nissa/prj_nivviks.conf
+++ b/zephyr/projects/nissa/prj_nivviks.conf
@@ -79,6 +79,32 @@ CONFIG_SYSCON=y
 CONFIG_PLATFORM_EC_CBI_EEPROM=y
 CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
 
+# USB-C/PD
+CONFIG_PLATFORM_EC_USBC=y
+CONFIG_PLATFORM_EC_USB_VID=0x18d1
+CONFIG_PLATFORM_EC_USB_PID=0x505a
+CONFIG_PLATFORM_EC_USB_PD_PORT_MAX_COUNT=2
+
+# TCPC+PPC: both C0 and C1 are RAA489000, but C1 may not be present
+CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y
+
+CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
+CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
+
+# TODO(b/211693800): configure USB retimers
+
+# Charger/battery
+CONFIG_PLATFORM_EC_BATTERY=y
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+
+CONFIG_PLATFORM_EC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGER_RAA489000=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+
 # TODO(b/188605676): bring these features up
 CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
 
diff --git a/zephyr/projects/nissa/src/charger.c b/zephyr/projects/nissa/src/charger.c
new file mode 100644
index 0000000000..32dff4c403
--- /dev/null
+++ b/zephyr/projects/nissa/src/charger.c
@@ -0,0 +1,37 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "usb_pd.h"
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0_TCPC,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+	/*
+	 * TODO(b:212490923) port 1 is present on sub-boards 1 and 2 with same
+	 * configuration as port 0 but on I2C_PORT_USB_C1_TCPC.
+	 */
+};
+const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = raa489000_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/zephyr/projects/nissa/src/usbc.c b/zephyr/projects/nissa/src/usbc.c
new file mode 100644
index 0000000000..4fd2335d01
--- /dev/null
+++ b/zephyr/projects/nissa/src/usbc.c
@@ -0,0 +1,286 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state_v2.h"
+#include "chipset.h"
+#include "hooks.h"
+#include "usb_mux.h"
+#include "usbc_ppc.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/tcpm/raa489000.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+
+struct ppc_config_t ppc_chips[] = {};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.drv = &raa489000_tcpm_drv,
+		/* RAA489000 implements TCPCI 2.0 */
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	/*
+	 * TODO(b:212490923) port 1 is present on sub-boards 1 and 2 with same
+	 * configuration as port 0 but on I2C_PORT_USB_C1_TCPC.
+	 */
+};
+
+struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.usb_port = 0,
+		.driver = &virtual_usb_mux_driver,
+		.hpd_update = &virtual_hpd_update,
+	},
+	/*
+	 * TODO(b:212490923) port 1 is present on sub-boards 1 and 2 with same
+	 * configuration.
+	 */
+};
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	/* TODO(b:212490923) enable port 1 if present (by returning 2). */
+	return 1;
+}
+
+void board_set_charge_limit(int port, int supplier, int charge_ma,
+			    int max_ma, int charge_mv)
+{
+	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
+
+	/*
+	 * Assume charger overdraws by about 4%, keeping the actual draw
+	 * within spec. This adjustment can be changed with characterization
+	 * of actual hardware.
+	 */
+	icl = icl * 96 / 100;
+	charge_set_input_current_limit(icl, charge_mv);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 &&
+			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	/* TODO(b:212490923) ignore C1 interrupts if port is not present. */
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): could send a reset command to the TCPC here
+	 * if needed.
+	 */
+}
+
+/*
+ * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible
+ * for an interrupt to be lost if one asserts the IRQ, the other does the same
+ * then the first releases it: there will only be one falling edge to trigger
+ * the interrupt, and the line will be held low. We handle this by running a
+ * deferred check after a falling edge to see whether the IRQ is still being
+ * asserted. If it is, we assume an interrupt may have been lost and we need
+ * to poll each chip for events again.
+ */
+#define USBC_INT_POLL_DELAY_US 5000
+
+static void poll_c0_int(void);
+DECLARE_DEFERRED(poll_c0_int);
+static void poll_c1_int(void);
+DECLARE_DEFERRED(poll_c1_int);
+
+static void usbc_interrupt_trigger(int port)
+{
+	schedule_deferred_pd_interrupt(port);
+	task_set_event(PD_PORT_TO_TASK_ID(port), USB_CHG_EVENT_BC12);
+}
+
+#define USBC_INT_POLL_DATA(port) poll_c ## port ## _int_data
+#define USBC_INT_POLL(port)						  \
+	static void poll_c ## port ## _int (void)			  \
+	{								  \
+		if (!gpio_get_level(GPIO_USB_C ## port ## _PD_INT_ODL)) { \
+			usbc_interrupt_trigger(port);			  \
+			hook_call_deferred(&USBC_INT_POLL_DATA(port),	  \
+					   USBC_INT_POLL_DELAY_US);	  \
+		}							  \
+	}
+
+USBC_INT_POLL(0)
+USBC_INT_POLL(1)
+
+void usb_c0_interrupt(enum gpio_signal gpio)
+{
+	/*
+	 * We've just been called from a falling edge, so there's definitely
+	 * no lost IRQ right now. Cancel any pending check.
+	 */
+	hook_call_deferred(&USBC_INT_POLL_DATA(0), -1);
+	/* Trigger polling of TCPC and BC1.2 in respective tasks */
+	usbc_interrupt_trigger(0);
+	/* Check for lost interrupts in a bit */
+	hook_call_deferred(&USBC_INT_POLL_DATA(0), USBC_INT_POLL_DELAY_US);
+}
+
+void usb_c1_interrupt(enum gpio_signal gpio)
+{
+	hook_call_deferred(&USBC_INT_POLL_DATA(1), -1);
+	usbc_interrupt_trigger(1);
+	hook_call_deferred(&USBC_INT_POLL_DATA(1), USBC_INT_POLL_DELAY_US);
+}
+
+static void usbc_init(void)
+{
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, usbc_init, HOOK_PRIO_DEFAULT);