Remove ryu P4/P5 support

Remove ryu_p4p5 EC board code along the "splitted" Sensor hub board
(ryu_sh/ryu_sh_loader): It's time to get rid of oldies.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=smaug
BUG=chrome-os-partner:38333
TEST=make buildall
CQ-DEPEND=*I6df51d7b4be2be7217604da60462b8c9d0cde1d2

Change-Id: Iebc4022267afccb5057c856d624e56a850ecbd70
Reviewed-on: https://chromium-review.googlesource.com/286780
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>

22 files changed, 0 insertions, 1891 deletions

diff --git a/board/ryu_p4p5/Makefile b/board/ryu_p4p5/Makefile
deleted file mode 120000
index 94aaae2c4d..0000000000
--- a/board/ryu_p4p5/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-../../Makefile
\ No newline at end of file
diff --git a/board/ryu_p4p5/board.c b/board/ryu_p4p5/board.c
deleted file mode 100644
index 34f6b3be42..0000000000
--- a/board/ryu_p4p5/board.c
+++ /dev/null
@@ -1,516 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* ryu board configuration */
-
-#include "adc.h"
-#include "adc_chip.h"
-#include "atomic.h"
-#include "battery.h"
-#include "case_closed_debug.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "common.h"
-#include "console.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "inductive_charging.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "usb.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_spi.h"
-#include "usb-stm32f3.h"
-#include "usb-stream.h"
-#include "usart-stm32f3.h"
-#include "util.h"
-#include "pi3usb9281.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-/* VBUS too low threshold */
-#define VBUS_LOW_THRESHOLD_MV 4600
-
-/* Input current error margin */
-#define IADP_ERROR_MARGIN_MA 100
-
-static int charge_current_limit;
-
-/*
- * PD host event status for host command
- * Note: this variable must be aligned on 4-byte boundary because we pass the
- * address to atomic_ functions which use assembly to access them.
- */
-static struct ec_response_host_event_status host_event_status __aligned(4);
-
-/*
- * Store the state of our USB data switches so that they can be restored
- * after pericom reset.
- */
-static int usb_switch_state;
-
-static void vbus_log(void)
-{
-	CPRINTS("VBUS %d", gpio_get_level(GPIO_CHGR_ACOK));
-}
-DECLARE_DEFERRED(vbus_log);
-
-void vbus_evt(enum gpio_signal signal)
-{
-	struct charge_port_info charge;
-	int vbus_level = gpio_get_level(signal);
-
-	/*
-	 * If VBUS is low, or VBUS is high and we are not outputting VBUS
-	 * ourselves, then update the VBUS supplier.
-	 */
-	if (!vbus_level || !gpio_get_level(GPIO_USBC_5V_EN)) {
-		charge.voltage = USB_CHARGER_VOLTAGE_MV;
-		charge.current = vbus_level ? USB_CHARGER_MIN_CURR_MA : 0;
-		charge_manager_update_charge(CHARGE_SUPPLIER_VBUS, 0, &charge);
-	}
-
-	hook_call_deferred(vbus_log, 0);
-	if (task_start_called())
-		task_wake(TASK_ID_PD);
-}
-
-void usb_evt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_USB_CHG_P0);
-}
-
-#include "gpio_list.h"
-
-const void *const usb_strings[] = {
-	[USB_STR_DESC]           = usb_string_desc,
-	[USB_STR_VENDOR]         = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]        = USB_STRING_DESC("Ryu debug"),
-	[USB_STR_VERSION]        = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_CONSOLE_NAME]   = USB_STRING_DESC("EC_PD"),
-	[USB_STR_AP_STREAM_NAME] = USB_STRING_DESC("AP"),
-	[USB_STR_SH_STREAM_NAME] = USB_STRING_DESC("SH"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-/*
- * Define AP and SH console forwarding queues and associated USART and USB
- * stream endpoints.
- */
-static struct usart_config const ap_usart;
-static struct usart_config const sh_usart;
-
-struct usb_stream_config const ap_usb;
-struct usb_stream_config const sh_usb;
-
-static struct queue const ap_usart_to_usb = QUEUE_DIRECT(64, uint8_t,
-							 ap_usart.producer,
-							 ap_usb.consumer);
-static struct queue const ap_usb_to_usart = QUEUE_DIRECT(64, uint8_t,
-							 ap_usb.producer,
-							 ap_usart.consumer);
-static struct queue const sh_usart_to_usb = QUEUE_DIRECT(64, uint8_t,
-							 sh_usart.producer,
-							 sh_usb.consumer);
-static struct queue const sh_usb_to_usart = QUEUE_DIRECT(64, uint8_t,
-							 sh_usb.producer,
-							 sh_usart.consumer);
-
-static struct usart_config const ap_usart = USART_CONFIG(usart1_hw,
-							 usart_rx_interrupt,
-							 usart_tx_interrupt,
-							 115200,
-							 ap_usart_to_usb,
-							 ap_usb_to_usart);
-
-static struct usart_config const sh_usart = USART_CONFIG(usart3_hw,
-							 usart_rx_interrupt,
-							 usart_tx_interrupt,
-							 115200,
-							 sh_usart_to_usb,
-							 sh_usb_to_usart);
-
-#define AP_USB_STREAM_RX_SIZE	16
-#define AP_USB_STREAM_TX_SIZE	16
-
-USB_STREAM_CONFIG(ap_usb,
-		  USB_IFACE_AP_STREAM,
-		  USB_STR_AP_STREAM_NAME,
-		  USB_EP_AP_STREAM,
-		  AP_USB_STREAM_RX_SIZE,
-		  AP_USB_STREAM_TX_SIZE,
-		  ap_usb_to_usart,
-		  ap_usart_to_usb)
-
-#define SH_USB_STREAM_RX_SIZE	16
-#define SH_USB_STREAM_TX_SIZE	16
-
-USB_STREAM_CONFIG(sh_usb,
-		  USB_IFACE_SH_STREAM,
-		  USB_STR_SH_STREAM_NAME,
-		  USB_EP_SH_STREAM,
-		  SH_USB_STREAM_RX_SIZE,
-		  SH_USB_STREAM_TX_SIZE,
-		  sh_usb_to_usart,
-		  sh_usart_to_usb)
-
-struct pi3usb9281_config pi3usb9281_chips[] = {
-	{
-		.i2c_port = I2C_PORT_PERICOM,
-		.mux_lock = NULL,
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
-	     CONFIG_USB_SWITCH_PI3USB9281_CHIP_COUNT);
-
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = {
-	{
-		.port_addr = 0,
-		.driver    = &p5_board_custom_usb_mux_driver,
-	},
-};
-
-/* Initialize board. */
-static void board_init(void)
-{
-	struct charge_port_info charge_none, charge_vbus;
-
-	/* Select P4 driver for old boards due to different GPIO config */
-	if (board_get_version() < 5)
-		usb_muxes[0].driver = &p4_board_custom_usb_mux_driver;
-
-	/* Initialize all pericom charge suppliers to 0 */
-	charge_none.voltage = USB_CHARGER_VOLTAGE_MV;
-	charge_none.current = 0;
-	charge_manager_update_charge(CHARGE_SUPPLIER_PROPRIETARY,
-				     0,
-				     &charge_none);
-	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_CDP, 0, &charge_none);
-	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_DCP, 0, &charge_none);
-	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_SDP, 0, &charge_none);
-	charge_manager_update_charge(CHARGE_SUPPLIER_OTHER, 0, &charge_none);
-
-	/* Initialize VBUS supplier based on whether or not VBUS is present */
-	charge_vbus.voltage = USB_CHARGER_VOLTAGE_MV;
-	charge_vbus.current = USB_CHARGER_MIN_CURR_MA;
-	if (gpio_get_level(GPIO_CHGR_ACOK))
-		charge_manager_update_charge(CHARGE_SUPPLIER_VBUS, 0,
-					     &charge_vbus);
-	else
-		charge_manager_update_charge(CHARGE_SUPPLIER_VBUS, 0,
-					     &charge_none);
-
-	/* Enable pericom BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USBC_BC12_INT_L);
-
-	/*
-	 * Determine recovery mode is requested by the power, volup, and
-	 * voldown buttons being pressed.
-	 */
-	if (power_button_signal_asserted() &&
-	    !gpio_get_level(GPIO_BTN_VOLD_L) &&
-	    !gpio_get_level(GPIO_BTN_VOLU_L))
-		host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY);
-
-	/*
-	 * Initialize AP and SH console forwarding USARTs and queues.
-	 */
-	queue_init(&ap_usart_to_usb);
-	queue_init(&ap_usb_to_usart);
-	queue_init(&sh_usart_to_usb);
-	queue_init(&sh_usb_to_usart);
-	usart_init(&ap_usart);
-	usart_init(&sh_usart);
-
-	/*
-	 * Enable CC lines after all GPIO have been initialized. Note, it is
-	 * important that this is enabled after the CC_DEVICE_ODL lines are
-	 * set low to specify device mode.
-	 */
-	gpio_set_level(GPIO_USBC_CC_EN, 1);
-
-	/* Enable interrupts on VBUS transitions. */
-	gpio_enable_interrupt(GPIO_CHGR_ACOK);
-
-	/*
-	 * TODO(crosbug.com/p/38689) Workaround for PMIC issue on P5.
-	 * remove when P5 are de-commissioned.
-	 * We are re-using EXTINT1 for the new power sequencing workaround
-	 * this is killing the base closing detection on P5
-	 * we won't charge it.
-	 */
-	if (board_get_version() == 5)
-		gpio_enable_interrupt(GPIO_HPD_IN);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_HOLD, 1, "AP_HOLD"},
-	{GPIO_AP_IN_SUSPEND,  1, "SUSPEND_ASSERTED"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/*
- * TODO(crosbug.com/p/38689) Workaround for MAX77620 PMIC EN_PP3300 issue.
- * remove when P5 are de-commissioned.
- */
-void pp1800_on_off_evt(enum gpio_signal signal)
-{
-	int level = gpio_get_level(signal);
-	gpio_set_level(GPIO_EN_PP3300_RSVD, level);
-}
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Vbus sensing. Converted to mV, /10 voltage divider. */
-	[ADC_VBUS] = {"VBUS",  30000, 4096, 0, STM32_AIN(0)},
-	/* USB PD CC lines sensing. Converted to mV (3000mV/4096). */
-	[ADC_CC1_PD] = {"CC1_PD", 3000, 4096, 0, STM32_AIN(1)},
-	[ADC_CC2_PD] = {"CC2_PD", 3000, 4096, 0, STM32_AIN(3)},
-	/* Charger current sensing. Converted to mA. */
-	[ADC_IADP] = {"IADP",  7500, 4096, 0, STM32_AIN(8)},
-	[ADC_IBAT] = {"IBAT", 37500, 4096, 0, STM32_AIN(13)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
-	{"slave",  I2C_PORT_SLAVE, 100,
-		GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-void board_set_usb_switches(int port, enum usb_switch setting)
-{
-	/* If switch is not changing, then return */
-	if (setting == usb_switch_state)
-		return;
-
-	if (setting != USB_SWITCH_RESTORE)
-		usb_switch_state = setting;
-	pi3usb9281_set_switches(port, usb_switch_state);
-}
-
-int extpower_is_present(void)
-{
-	return gpio_get_level(GPIO_CHGR_ACOK);
-}
-
-void usb_board_connect(void)
-{
-	gpio_set_level(GPIO_USB_PU_EN_L, 0);
-}
-
-void usb_board_disconnect(void)
-{
-	gpio_set_level(GPIO_USB_PU_EN_L, 1);
-}
-
-/**
- * Set active charge port -- only one port can be active at a time.
- *
- * @param charge_port   Charge port to enable.
- *
- * Returns EC_SUCCESS if charge port is accepted and made active,
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	int ret = EC_SUCCESS;
-	/* check if we are source vbus on that port */
-	int src = gpio_get_level(GPIO_USBC_5V_EN);
-
-	if (charge_port >= 0 && charge_port < CONFIG_USB_PD_PORT_COUNT && src) {
-		CPRINTS("Port %d is not a sink, skipping enable", charge_port);
-		charge_port = CHARGE_PORT_NONE;
-		ret = EC_ERROR_INVAL;
-	}
-	if (charge_port == CHARGE_PORT_NONE) {
-		/* Disable charging */
-		charge_set_input_current_limit(0);
-	}
-
-	return ret;
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param charge_ma     Desired charge limit (mA).
- */
-void board_set_charge_limit(int charge_ma)
-{
-	int rv;
-
-	charge_current_limit = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-	rv = charge_set_input_current_limit(charge_current_limit);
-	if (rv < 0)
-		CPRINTS("Failed to set input current limit for PD");
-}
-
-/* Send host event up to AP */
-void pd_send_host_event(int mask)
-{
-	/* mask must be set */
-	if (!mask)
-		return;
-
-	atomic_or(&(host_event_status.status), mask);
-	/* interrupt the AP */
-	host_set_single_event(EC_HOST_EVENT_PD_MCU);
-}
-
-/**
- * Return whether ramping is allowed for given supplier
- */
-int board_is_ramp_allowed(int supplier)
-{
-	return supplier == CHARGE_SUPPLIER_BC12_DCP ||
-	       supplier == CHARGE_SUPPLIER_BC12_SDP ||
-	       supplier == CHARGE_SUPPLIER_BC12_CDP ||
-	       supplier == CHARGE_SUPPLIER_PROPRIETARY;
-}
-
-/**
- * Return the maximum allowed input current
- */
-int board_get_ramp_current_limit(int supplier, int sup_curr)
-{
-	switch (supplier) {
-	case CHARGE_SUPPLIER_BC12_DCP:
-		return 2000;
-	case CHARGE_SUPPLIER_BC12_SDP:
-		return 1000;
-	case CHARGE_SUPPLIER_BC12_CDP:
-	case CHARGE_SUPPLIER_PROPRIETARY:
-		return sup_curr;
-	default:
-		return 500;
-	}
-}
-
-/**
- * Return if board is consuming full amount of input current
- */
-int board_is_consuming_full_charge(void)
-{
-	return adc_read_channel(ADC_IADP) >= charge_current_limit -
-					     IADP_ERROR_MARGIN_MA;
-}
-
-/**
- * Return if VBUS is sagging low enough that we should stop ramping
- */
-int board_is_vbus_too_low(enum chg_ramp_vbus_state ramp_state)
-{
-	return adc_read_channel(ADC_VBUS) < VBUS_LOW_THRESHOLD_MV;
-}
-
-/*
- * Enable and disable SPI for case closed debugging.  This forces the AP into
- * reset while SPI is enabled, thus preventing contention on the SPI interface.
- */
-void usb_spi_board_enable(struct usb_spi_config const *config)
-{
-	/* Place AP into reset */
-	gpio_set_level(GPIO_PMIC_WARM_RESET_L, 0);
-
-	/* Configure SPI GPIOs */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
-	gpio_set_flags(GPIO_SPI_FLASH_NSS, GPIO_OUT_HIGH);
-
-	/* Set all four SPI pins to high speed */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xf03c0000;
-
-	/* Enable clocks to SPI2 module */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Enable SPI LDO to power the flash chip */
-	gpio_set_level(GPIO_VDDSPI_EN, 1);
-
-	spi_enable(1);
-}
-
-void usb_spi_board_disable(struct usb_spi_config const *config)
-{
-	spi_enable(0);
-
-	/* Disable SPI LDO */
-	gpio_set_level(GPIO_VDDSPI_EN, 0);
-
-	/* Disable clocks to SPI2 module */
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Release SPI GPIOs */
-	gpio_config_module(MODULE_SPI_MASTER, 0);
-	gpio_set_flags(GPIO_SPI_FLASH_NSS, GPIO_INPUT);
-
-	/* Release AP from reset */
-	gpio_set_level(GPIO_PMIC_WARM_RESET_L, 1);
-}
-
-int board_get_version(void)
-{
-	static int ver;
-
-	if (!ver) {
-		/*
-		 * read the board EC ID on the tristate strappings
-		 * using ternary encoding: 0 = 0, 1 = 1, Hi-Z = 2
-		 */
-		uint8_t id0 = 0, id1 = 0;
-		gpio_set_flags(GPIO_BOARD_ID0, GPIO_PULL_DOWN | GPIO_INPUT);
-		gpio_set_flags(GPIO_BOARD_ID1, GPIO_PULL_DOWN | GPIO_INPUT);
-		usleep(100);
-		id0 = gpio_get_level(GPIO_BOARD_ID0);
-		id1 = gpio_get_level(GPIO_BOARD_ID1);
-		gpio_set_flags(GPIO_BOARD_ID0, GPIO_PULL_UP | GPIO_INPUT);
-		gpio_set_flags(GPIO_BOARD_ID1, GPIO_PULL_UP | GPIO_INPUT);
-		usleep(100);
-		id0 = gpio_get_level(GPIO_BOARD_ID0) && !id0 ? 2 : id0;
-		id1 = gpio_get_level(GPIO_BOARD_ID1) && !id1 ? 2 : id1;
-		gpio_set_flags(GPIO_BOARD_ID0, GPIO_INPUT);
-		gpio_set_flags(GPIO_BOARD_ID1, GPIO_INPUT);
-		ver = id1 * 3 + id0;
-		CPRINTS("Board ID = %d\n", ver);
-	}
-
-	return ver;
-}
-
-/****************************************************************************/
-/* Host commands */
-
-static int host_event_status_host_cmd(struct host_cmd_handler_args *args)
-{
-	struct ec_response_host_event_status *r = args->response;
-
-	/* Read and clear the host event status to return to AP */
-	r->status = atomic_read_clear(&(host_event_status.status));
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PD_HOST_EVENT_STATUS, host_event_status_host_cmd,
-			EC_VER_MASK(0));
diff --git a/board/ryu_p4p5/board.h b/board/ryu_p4p5/board.h
deleted file mode 100644
index 3602700f23..0000000000
--- a/board/ryu_p4p5/board.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ryu board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART2 (PD4/PD5) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 2
-
-/* By default, enable all console messages excepted USB */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_USB) | CC_MASK(CC_LIGHTBAR)))
-
-/* Optional features */
-#undef CONFIG_CMD_HASH
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP
-#define CONFIG_CMD_CHGRAMP
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_POWER_DELIVERY
-#undef  CONFIG_USB_PD_DEBUG_DR
-#define CONFIG_USB_PD_DEBUG_DR PD_ROLE_UFP
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_FLASH_ERASE_CHECK
-#define CONFIG_USB_PD_INTERNAL_COMP
-#define CONFIG_USB_PD_PORT_COUNT 1
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_USB_SWITCH_PI3USB9281
-#define CONFIG_USB_SWITCH_PI3USB9281_CHIP_COUNT 1
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_ADC
-#define CONFIG_ADC_SAMPLE_TIME 3
-#define CONFIG_HW_CRC
-#define CONFIG_I2C
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_MKBP_EVENT
-#define CONFIG_VBOOT_HASH
-#define CONFIG_WATCHDOG_HELP
-#undef CONFIG_TASK_PROFILING
-#define CONFIG_INDUCTIVE_CHARGING
-#undef CONFIG_HIBERNATE
-#undef CONFIG_UART_TX_DMA /* DMAC_CH7 is used by USB PD */
-#define CONFIG_UART_RX_DMA
-#define CONFIG_UART_RX_DMA_CH STM32_DMAC_USART2_RX
-
-/* Charging/Power configuration */
-#define CONFIG_BATTERY_RYU
-#define CONFIG_BATTERY_BQ27541
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_V2
-#define CONFIG_CHARGER_BQ24773
-#define CONFIG_CHARGER_ILIM_PIN_DISABLED
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_SENSE_RESISTOR 5
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHIPSET_TEGRA
-#define CONFIG_PMIC_FW_LONG_PRESS_TIMER
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_ACTIVE_STATE 1
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-
-/* I2C ports configuration */
-#define I2C_PORT_MASTER 0
-#define I2C_PORT_SLAVE  1
-#define I2C_PORT_EC I2C_PORT_SLAVE
-#define I2C_PORT_CHARGER I2C_PORT_MASTER
-#define I2C_PORT_BATTERY I2C_PORT_MASTER
-#define I2C_PORT_LIGHTBAR I2C_PORT_MASTER
-#define I2C_PORT_PERICOM I2C_PORT_MASTER
-
-/* slave address for host commands */
-#ifdef HAS_TASK_HOSTCMD
-#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR 0x3c
-#endif
-
-/* USART and USB stream drivers */
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART1
-#define CONFIG_STREAM_USART3
-#define CONFIG_STREAM_USB
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_PID 0x500f
-
-/* Prevent the USB driver from initializing at boot */
-#define CONFIG_USB_INHIBIT_INIT
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE   0
-#define USB_IFACE_AP_STREAM 1
-#define USB_IFACE_SH_STREAM 2
-#define USB_IFACE_SPI       3
-#define USB_IFACE_COUNT     4
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_CONSOLE   1
-#define USB_EP_AP_STREAM 2
-#define USB_EP_SH_STREAM 3
-#define USB_EP_SPI       4
-#define USB_EP_COUNT     5
-
-/* Enable console over USB */
-#define CONFIG_USB_CONSOLE
-
-/* Enable control of SPI over USB */
-#define CONFIG_SPI_MASTER_PORT 2
-#define CONFIG_SPI_CS_GPIO     GPIO_SPI_FLASH_NSS
-
-#define CONFIG_USB_SPI
-
-/* Enable Case Closed Debugging */
-#define CONFIG_CASE_CLOSED_DEBUG
-
-/* Maximum number of deferrable functions */
-#undef  DEFERRABLE_MAX_COUNT
-#define DEFERRABLE_MAX_COUNT 14
-
-#ifndef __ASSEMBLER__
-
-int board_get_version(void);
-
-/* Timer selection */
-#define TIM_CLOCK32 5
-#define TIM_WATCHDOG 19
-
-#include "gpio_signal.h"
-
-/* PMIC_THERM_L selection at runtime depending on board version */
-#define GPIO_PMIC_THERM_L (board_get_version() >= 5 ? GPIO_P5_PMIC_THERM_L : \
-						      GPIO_P4_PMIC_THERM_L)
-
-enum power_signal {
-	TEGRA_XPSHOLD = 0,
-	TEGRA_SUSPEND_ASSERTED,
-
-	/* Number of power signals */
-	POWER_SIGNAL_COUNT
-};
-
-/* ADC signal */
-enum adc_channel {
-	ADC_VBUS = 0,
-	ADC_CC1_PD,
-	ADC_CC2_PD,
-	ADC_IADP,
-	ADC_IBAT,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_VERSION,
-	USB_STR_CONSOLE_NAME,
-	USB_STR_AP_STREAM_NAME,
-	USB_STR_SH_STREAM_NAME,
-
-	USB_STR_COUNT
-};
-
-/* VBUS enable GPIO */
-#define GPIO_USB_C0_5V_EN GPIO_USBC_5V_EN
-
-/* 1.5A Rp */
-#define PD_SRC_VNC            PD_SRC_1_5_VNC_MV
-#define PD_SRC_RD_THRESHOLD   PD_SRC_1_5_RD_THRESH_MV
-
-/* start as a sink in case we have no other power supply/battery */
-#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED
-
-/* delay for the voltage transition on the power supply, chip max is 16us */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  20000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 20000 /* us */
-
-/* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 10000
-#define PD_MAX_POWER_MW       24000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
-
-/* The lower the input voltage, the higher the power efficiency. */
-#define PD_PREFER_LOW_VOLTAGE
-
-/* Mux driver functions differ by board revision */
-extern const struct usb_mux_driver p4_board_custom_usb_mux_driver;
-extern const struct usb_mux_driver p5_board_custom_usb_mux_driver;
-
-/* Set the charge current limit. */
-void board_set_charge_limit(int charge_ma);
-
-/* PP1800 transition GPIO interrupt handler */
-void pp1800_on_off_evt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/ryu_p4p5/build.mk b/board/ryu_p4p5/build.mk
deleted file mode 100644
index 7d6e69851d..0000000000
--- a/board/ryu_p4p5/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F373VB
-CHIP:=stm32
-CHIP_FAMILY:=stm32f3
-CHIP_VARIANT:=stm32f373
-
-board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_mux.o usb_pd_policy.o
diff --git a/board/ryu_p4p5/ec.tasklist b/board/ryu_p4p5/ec.tasklist
deleted file mode 100644
index 373e6e09b8..0000000000
--- a/board/ryu_p4p5/ec.tasklist
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * List of enabled tasks in the priority order
- *
- * The first one has the lowest priority.
- *
- * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
- * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
- * where :
- * 'n' in the name of the task
- * 'r' in the main routine of the task
- * 'd' in an opaque parameter passed to the routine at startup
- * 's' is the stack size in bytes; must be a multiple of 8
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, SMALLER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, \
-		    SMALLER_TASK_STACK_SIZE) \
-	TASK_NOTEST(LIGHTBAR, lightbar_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/ryu_p4p5/gpio.inc b/board/ryu_p4p5/gpio.inc
deleted file mode 100644
index ecd6451489..0000000000
--- a/board/ryu_p4p5/gpio.inc
+++ /dev/null
@@ -1,144 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupts */
-GPIO_INT(CHGR_ACOK,            PIN(D, 4),  GPIO_INT_BOTH | GPIO_PULL_UP,    vbus_evt)
-GPIO_INT(POWER_BUTTON_L,       PIN(C, 13), GPIO_INT_BOTH,                   power_button_interrupt) /* active high, the name is for compatibility with existing code */
-GPIO_INT(USBC_BC12_INT_L,      PIN(D, 11), GPIO_INT_FALLING | GPIO_PULL_UP, usb_evt)
-GPIO_INT(LID_OPEN,             PIN(E, 1),  GPIO_INT_BOTH | GPIO_PULL_UP,    lid_interrupt)
-GPIO_INT(CHARGE_DONE,          PIN(E, 6),  GPIO_INT_BOTH,                   inductive_charging_interrupt)
-GPIO_INT(AP_IN_SUSPEND,        PIN(F, 9),  GPIO_INT_BOTH,                   power_signal_interrupt)
-GPIO_INT(AP_HOLD,              PIN(E, 3),  GPIO_INT_BOTH,                   power_signal_interrupt)
-/*
- * TODO(crosbug.com/p/38689) Workaround for MAX77620 PMIC PP3300 issue
- * Put back as GPIO_ODR_HIGH for P6+
- */
-GPIO_INT(HPD_IN,               PIN(C, 1),  GPIO_INT_BOTH,                   pp1800_on_off_evt)
-
-/* Interrupt lines not used yet */
-GPIO(BC_TEMP_ALERT_L,      PIN(C, 5),  GPIO_INT_FALLING)
-GPIO(LB_INT_L,             PIN(E, 7),  GPIO_INT_FALLING | GPIO_PULL_UP)
-GPIO(LIGHTBAR_EN_L,        PIN(E, 8),  GPIO_INT_FALLING | GPIO_PULL_UP)
-GPIO(BASE_PRES_L,          PIN(E, 10), GPIO_INT_BOTH | GPIO_PULL_UP)
-
-/* Buttons */
-GPIO(BTN_VOLD_L,           PIN(C, 0),  GPIO_INPUT | GPIO_PULL_UP)
-GPIO(BTN_VOLU_L,           PIN(A, 2),  GPIO_INPUT | GPIO_PULL_UP)
-
-/* PD RX/TX */
-GPIO(USBC_CC1_PD,          PIN(A, 1),  GPIO_ANALOG)
-GPIO(USBC_CC2_PD,          PIN(A, 3),  GPIO_ANALOG)
-GPIO(USBC_CC_EN,           PIN(A, 4),  GPIO_OUT_LOW)
-GPIO(USBC_CC_TX_DATA,      PIN(A, 6),  GPIO_OUT_LOW)
-GPIO(USBC_CC_TX_EN,        PIN(D, 7),  GPIO_OUT_LOW)
-
-#if 0
-/* Alternate functions */
-GPIO(USBC_TX_CLKOUT,       PIN(B, 1),  GPIO_OUT_LOW)
-GPIO(USBC_TX_CLKIN,        PIN(B, 3),  GPIO_OUT_LOW)
-#endif
-
-/* System power */
-GPIO(PMIC_PWRON_L,         PIN(D, 14), GPIO_ODR_HIGH)
-GPIO(PMIC_WARM_RESET_L,    PIN(E, 4),  GPIO_ODR_HIGH)
-GPIO(EN_PP5000,            PIN(A, 14), GPIO_OUT_LOW) /* Proto 5+ */
-/*
- * We are missing an external pull-up for EN_PP3300.
- * This GPIO is used to pull it up through an external 100kOhm.
- * EN_PP3300 is still controlled by PMIC though.
- */
-GPIO(EN_PP3300_RSVD,       PIN(E, 13), GPIO_OUT_LOW)
-/* sensor temp output and PMIC reset input */
-GPIO(P5_PMIC_THERM_L,      PIN(B, 8),  GPIO_ODR_HIGH)
-/* TODO(crosbug.com/p/38333) remove P4_PMIC_THERM_L */
-GPIO(P4_PMIC_THERM_L,      PIN(D, 12), GPIO_ODR_HIGH)
-
-GPIO(VBUS_SENSE,           PIN(A, 0),  GPIO_ANALOG)
-GPIO(CHGR_IADP,            PIN(B, 0),  GPIO_ANALOG)
-GPIO(CHGR_IBAT,            PIN(C, 3),  GPIO_ANALOG)
-
-/* Inductive charging */
-GPIO(CHARGE_EN,            PIN(D, 13), GPIO_OUT_LOW)
-GPIO(BASE_CHG_VDD_EN,      PIN(E, 5),  GPIO_OUT_LOW)
-
-/* USB-C Power and muxes control */
-GPIO(USBC_CHARGE_EN_L,     PIN(A, 7),  GPIO_OUT_LOW)
-GPIO(USBC_5V_EN,           PIN(D, 8),  GPIO_OUT_LOW)
-GPIO(USBC_VCONN1_EN_L,     PIN(F, 10), GPIO_OUT_HIGH)
-GPIO(USBC_VCONN2_EN_L,     PIN(D, 10), GPIO_OUT_HIGH)
-
-GPIO(USBC_CC1_DEVICE_ODL,  PIN(A, 5),  GPIO_ODR_LOW)
-GPIO(USBC_CC2_DEVICE_ODL,  PIN(E, 14), GPIO_ODR_LOW)
-
-/* Pericom PI3USB30592 mux controls on Proto 5+ */
-GPIO(USBC_MUX_CONF0,       PIN(D, 3),  GPIO_OUT_LOW)
-GPIO(USBC_MUX_CONF1,       PIN(D, 9),  GPIO_OUT_LOW)
-GPIO(USBC_MUX_CONF2,       PIN(E, 0),  GPIO_OUT_LOW)
-/* TODO(crosbug.com/p/38333) remove USBC_DP_xxx GPIOs */
-GPIO(USBC_DP_MODE_L,       PIN(D, 1),  GPIO_OUT_HIGH)
-GPIO(USBC_DP_POLARITY,     PIN(D, 2),  GPIO_OUT_HIGH)
-
-/* Inputs */
-GPIO(BOARD_ID0,            PIN(E, 11),  GPIO_INPUT)
-GPIO(BOARD_ID1,            PIN(E, 12),  GPIO_INPUT)
-GPIO(SH_SIGNAL,            PIN(E, 2),   GPIO_INPUT)
-
-/* Lightbar reset */
-GPIO(LB_RST_L,             PIN(D, 15), GPIO_ODR_HIGH | GPIO_PULL_UP)
-
-#if 0
-/* Alternate functions */
-GPIO(USB_DM,               PIN(A, 11), GPIO_ANALOG)
-GPIO(USB_DP,               PIN(A, 12), GPIO_ANALOG)
-GPIO(UART_TX,              PIN(D, 5),  GPIO_OUT_LOW)
-GPIO(UART_RX,              PIN(D, 6),  GPIO_OUT_LOW)
-#endif
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(MASTER_I2C_SCL,       PIN(A, 15), GPIO_INPUT)
-GPIO(MASTER_I2C_SDA,       PIN(A, 14), GPIO_INPUT)
-GPIO(SLAVE_I2C_SCL,        PIN(A, 9),  GPIO_INPUT)
-GPIO(SLAVE_I2C_SDA,        PIN(A, 10), GPIO_INPUT)
-
-/* SCL gating for PI3USB9281 */
-GPIO(PERICOM_CLK_EN,       PIN(C, 15), GPIO_OUT_HIGH)
-
-/* Case closed debugging. */
-GPIO(USB_PU_EN_L,          PIN(C, 2),  GPIO_OUT_HIGH)
-GPIO(PD_DISABLE_DEBUG,     PIN(C, 6),  GPIO_OUT_LOW)
-GPIO(SPI_FLASH_NSS,        PIN(B, 9),  GPIO_INPUT)
-GPIO(VDDSPI_EN,            PIN(C, 12), GPIO_OUT_LOW)
-GPIO(SH_RESET,             PIN(C, 4),  GPIO_ODR_HIGH)
-GPIO(SH_BOOT,              PIN(C, 9),  GPIO_ODR_HIGH)
-GPIO(EC_INT_L,             PIN(F, 2),  GPIO_ODR_HIGH)
-GPIO(ENTERING_RW,          PIN(E, 15), GPIO_OUT_LOW)
-GPIO(WP_L,                 PIN(F, 6),  GPIO_INPUT)
-GPIO(FW_DEBUG_MODE_L,      PIN(C, 7),  GPIO_ODR_HIGH) /* Proto 5+ */
-
-#if 0
-/* Alternate functions */
-GPIO(SH_UART_TX,           PIN(C, 11), GPIO_OUT_LOW)
-GPIO(SH_UART_RX,           PIN(C, 10), GPIO_INPUT)
-GPIO(AP_UART_TX,           PIN(B, 6),  GPIO_OUT_LOW)
-GPIO(AP_UART_RX,           PIN(B, 7),  GPIO_INPUT)
-#endif
-
-UNIMPLEMENTED(AP_RESET_L)
-
-#define GPIO_ODR_UP	GPIO_OPEN_DRAIN | GPIO_PULL_UP
-
-ALTERNATE(PIN_MASK(B, 0xC400), 5, MODULE_SPI_MASTER, 0)            /* SPI2: PB10/14/15 */
-ALTERNATE(PIN_MASK(B, 0x0008), 5, MODULE_USB_PD,     0)            /* SPI1: SCK(PB3) */
-ALTERNATE(PIN_MASK(B, 0x0002), 2, MODULE_USB_PD,     0)            /* TIM3_CH4: PB1 */
-ALTERNATE(PIN_MASK(B, 0x00C0), 7, MODULE_USART,      0)            /* USART1: PB6/PB7 */
-ALTERNATE(PIN_MASK(D, 0x0060), 7, MODULE_UART,       GPIO_PULL_UP) /* USART2: PD4/PD5 */
-ALTERNATE(PIN_MASK(C, 0x0C00), 7, MODULE_USART,      GPIO_ODR_UP)  /* USART3: PC10/PC11 */
-ALTERNATE(PIN_MASK(A, 0xC600), 4, MODULE_I2C,        0)            /* I2C SLAVE:PA9/10 MASTER:PA14/15 */
-ALTERNATE(PIN_MASK(A, 0x1800),14, MODULE_USB,        0)            /* USB: PA11/12 */
diff --git a/board/ryu_p4p5/usb_mux.c b/board/ryu_p4p5/usb_mux.c
deleted file mode 100644
index 03689fc468..0000000000
--- a/board/ryu_p4p5/usb_mux.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Ryu-custom USB mux driver. */
-
-#include "common.h"
-#include "gpio.h"
-#include "usb_mux.h"
-#include "util.h"
-
-static int board_init_usb_mux(int port)
-{
-	return EC_SUCCESS;
-}
-
-static int board_set_usb_mux(int port, mux_state_t mux_state)
-{
-	/* reset everything */
-	gpio_set_level(GPIO_USBC_MUX_CONF0, 0);
-	gpio_set_level(GPIO_USBC_MUX_CONF1, 0);
-	gpio_set_level(GPIO_USBC_MUX_CONF2, 0);
-
-	if (!(mux_state & (MUX_USB_ENABLED | MUX_DP_ENABLED)))
-		/* everything is already disabled, we can return */
-		return EC_SUCCESS;
-
-	gpio_set_level(GPIO_USBC_MUX_CONF0, mux_state & MUX_POLARITY_INVERTED);
-
-	if (mux_state & MUX_USB_ENABLED)
-		/* USB 3.0 uses 2 superspeed lanes */
-		gpio_set_level(GPIO_USBC_MUX_CONF2, 1);
-
-	if (mux_state & MUX_DP_ENABLED)
-		/* DP uses available superspeed lanes (x2 or x4) */
-		gpio_set_level(GPIO_USBC_MUX_CONF1, 1);
-
-	return EC_SUCCESS;
-}
-
-/* TODO(crosbug.com/p/38333) remove me */
-#define GPIO_USBC_SS1_USB_MODE_L GPIO_USBC_MUX_CONF0
-#define GPIO_USBC_SS2_USB_MODE_L GPIO_USBC_MUX_CONF1
-#define GPIO_USBC_SS_EN_L GPIO_USBC_MUX_CONF2
-
-static int p4_board_set_usb_mux(int port, mux_state_t mux_state)
-{
-	int polarity = mux_state & MUX_POLARITY_INVERTED;
-
-	/* reset everything */
-	gpio_set_level(GPIO_USBC_SS_EN_L, 1);
-	gpio_set_level(GPIO_USBC_DP_MODE_L, 1);
-	gpio_set_level(GPIO_USBC_DP_POLARITY, 1);
-	gpio_set_level(GPIO_USBC_SS1_USB_MODE_L, 1);
-	gpio_set_level(GPIO_USBC_SS2_USB_MODE_L, 1);
-
-	if (!(mux_state & (MUX_USB_ENABLED | MUX_DP_ENABLED)))
-		/* everything is already disabled, we can return */
-		return EC_SUCCESS;
-
-	if (mux_state & MUX_USB_ENABLED)
-		/* USB 3.0 uses 2 superspeed lanes */
-		gpio_set_level(polarity ? GPIO_USBC_SS2_USB_MODE_L :
-					  GPIO_USBC_SS1_USB_MODE_L, 0);
-
-	if (mux_state & MUX_DP_ENABLED) {
-		/* DP uses available superspeed lanes (x2 or x4) */
-		gpio_set_level(GPIO_USBC_DP_POLARITY, polarity);
-		gpio_set_level(GPIO_USBC_DP_MODE_L, 0);
-	}
-
-	/* switch on superspeed lanes */
-	gpio_set_level(GPIO_USBC_SS_EN_L, 0);
-
-	return EC_SUCCESS;
-}
-
-static int board_get_usb_mux(int port, mux_state_t *mux_state)
-{
-	*mux_state = 0;
-
-	if (gpio_get_level(GPIO_USBC_MUX_CONF2))
-		*mux_state |= MUX_USB_ENABLED;
-	if (gpio_get_level(GPIO_USBC_MUX_CONF1))
-		*mux_state |= MUX_DP_ENABLED;
-	if (gpio_get_level(GPIO_USBC_MUX_CONF0))
-		*mux_state |= MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-static int p4_board_get_usb_mux(int port, mux_state_t *mux_state)
-{
-	*mux_state = 0;
-
-	if (!gpio_get_level(GPIO_USBC_SS1_USB_MODE_L) ||
-	    !gpio_get_level(GPIO_USBC_SS2_USB_MODE_L))
-		*mux_state |= MUX_USB_ENABLED;
-
-	if (!gpio_get_level(GPIO_USBC_DP_MODE_L))
-		*mux_state |= MUX_DP_ENABLED;
-
-	if (gpio_get_level(GPIO_USBC_DP_POLARITY))
-		*mux_state |= MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver p4_board_custom_usb_mux_driver = {
-	.init = board_init_usb_mux,
-	.set = p4_board_set_usb_mux,
-	.get = p4_board_get_usb_mux,
-};
-
-const struct usb_mux_driver p5_board_custom_usb_mux_driver = {
-	.init = board_init_usb_mux,
-	.set = board_set_usb_mux,
-	.get = board_get_usb_mux,
-};
-
diff --git a/board/ryu_p4p5/usb_pd_config.h b/board/ryu_p4p5/usb_pd_config.h
deleted file mode 100644
index 7a4df7a6a1..0000000000
--- a/board/ryu_p4p5/usb_pd_config.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-#include "adc.h"
-#include "charge_state.h"
-#include "clock.h"
-#include "gpio.h"
-#include "registers.h"
-#include "usb_mux.h"
-
-/* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX_C0 3
-#define TIM_CLOCK_PD_RX_C0 2
-
-#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
-#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
-
-/* Timer channel */
-#define TIM_RX_CCR_C0 4
-#define TIM_TX_CCR_C0 4
-
-/* RX timer capture/compare register */
-#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
-#define TIM_RX_CCR_REG(p) TIM_CCR_C0
-
-/* TX and RX timer register */
-#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
-#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
-#define TIM_REG_TX(p) TIM_REG_TX_C0
-#define TIM_REG_RX(p) TIM_REG_RX_C0
-
-/* use the hardware accelerator for CRC */
-#define CONFIG_HW_CRC
-
-/* TX is using SPI1 on PA6, PB3, and PB5 */
-#define SPI_REGS(p) STM32_SPI1_REGS
-
-static inline void spi_enable_clock(int port)
-{
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-}
-
-#define DMAC_SPI_TX(p) STM32_DMAC_CH3
-
-/* RX is using COMP1 triggering TIM2 CH4 */
-#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM2_IC4
-#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM2_IC4
-
-#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
-#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) ((1 << 21) | (1 << 22))
-#define IRQ_COMP STM32_IRQ_COMP
-/* triggers packet detection on comparator falling edge */
-#define EXTI_XTSR STM32_EXTI_FTSR
-
-#define DMAC_TIM_RX(p) STM32_DMAC_CH7
-
-/* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(int port)
-{
-	/* 40 MHz pin speed on SPI MISO PA6 */
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0x00003000;
-	/* 40 MHz pin speed on TIM3_CH4 (PB1) */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x0000000C;
-}
-
-/* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(int port)
-{
-	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= (1 << 12);
-	STM32_RCC_APB2RSTR &= ~(1 << 12);
-}
-
-/* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int port, int polarity)
-{
-	/* put SPI function on TX pin : PA6 is SPI MISO */
-	gpio_set_alternate_function(GPIO_A, 0x0040, 5);
-
-	/* set the low level reference */
-	gpio_set_level(GPIO_USBC_CC_TX_EN, 1);
-}
-
-/* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int port, int polarity)
-{
-	/* output low on SPI TX (PA6 is SPI1 MISO) to disable the FET */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-					& ~(3 << (2*6)))
-					|  (1 << (2*6));
-
-	/* put the low level reference in Hi-Z */
-	gpio_set_level(GPIO_USBC_CC_TX_EN, 0);
-}
-
-/* we know the plug polarity, do the right configuration */
-static inline void pd_select_polarity(int port, int polarity)
-{
-	/*
-	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
-	 *                            CC2 -> PA3 (COMP2 INP)
-	 * use VrefInt / 2 as INM (about 600mV)
-	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR
-		 & ~(STM32_COMP_CMP1INSEL_MASK | STM32_COMP_CMP2INSEL_MASK
-		   | STM32_COMP_CMP1EN | STM32_COMP_CMP2EN))
-		| STM32_COMP_CMP1INSEL_VREF12 | STM32_COMP_CMP2INSEL_VREF12
-		| (polarity ? STM32_COMP_CMP2EN : STM32_COMP_CMP1EN);
-}
-
-/* Initialize pins used for TX and put them in Hi-Z */
-static inline void pd_tx_init(void)
-{
-	gpio_config_module(MODULE_USB_PD, 1);
-}
-
-static inline void pd_set_host_mode(int port, int enable)
-{
-	if (enable) {
-		/* Turn the 5V regulator providing VBUS */
-		gpio_set_level(GPIO_EN_PP5000, 1);
-		/* We never charging in power source mode */
-		gpio_set_level(GPIO_USBC_CHARGE_EN_L, 1);
-		charge_set_input_current_limit(0);
-		/* High-Z is used for host mode. */
-		gpio_set_level(GPIO_USBC_CC1_DEVICE_ODL, 1);
-		gpio_set_level(GPIO_USBC_CC2_DEVICE_ODL, 1);
-	} else {
-		/* Kill VBUS power supply */
-		gpio_set_level(GPIO_USBC_5V_EN, 0);
-		/* Turn off the 5V regulator */
-		gpio_set_level(GPIO_EN_PP5000, 0);
-		/* Pull low for device mode. */
-		gpio_set_level(GPIO_USBC_CC1_DEVICE_ODL, 0);
-		gpio_set_level(GPIO_USBC_CC2_DEVICE_ODL, 0);
-		gpio_set_level(GPIO_USBC_CHARGE_EN_L, 0);
-	}
-
-}
-
-/**
- * Initialize various GPIOs and interfaces to safe state at start of pd_task.
- *
- * These include:
- *   VBUS, charge path based on power role.
- *   Physical layer CC transmit.
- *   VCONNs disabled.
- *
- * @param port        USB-C port number
- * @param power_role  Power role of device
- */
-static inline void pd_config_init(int port, uint8_t power_role)
-{
-	/*
-	 * Set CC pull resistors, and charge_en and vbus_en GPIOs to match
-	 * the initial role.
-	 */
-	pd_set_host_mode(port, power_role);
-
-	/* Initialize TX pins and put them in Hi-Z */
-	pd_tx_init();
-
-	/* Reset mux ... for NONE polarity doesn't matter */
-	usb_mux_set(port, TYPEC_MUX_NONE, USB_SWITCH_DISCONNECT, 0);
-
-	gpio_set_level(GPIO_USBC_VCONN1_EN_L, 1);
-	gpio_set_level(GPIO_USBC_VCONN2_EN_L, 1);
-}
-
-static inline int pd_adc_read(int port, int cc)
-{
-	if (cc == 0)
-		return adc_read_channel(ADC_CC1_PD);
-	else
-		return adc_read_channel(ADC_CC2_PD);
-}
-
-static inline void pd_set_vconn(int port, int polarity, int enable)
-{
-	/* Set VCONN on the opposite CC line from the polarity */
-	gpio_set_level(polarity ? GPIO_USBC_VCONN1_EN_L :
-				  GPIO_USBC_VCONN2_EN_L, !enable);
-}
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */
diff --git a/board/ryu_p4p5/usb_pd_policy.c b/board/ryu_p4p5/usb_pd_policy.c
deleted file mode 100644
index 4962a4d044..0000000000
--- a/board/ryu_p4p5/usb_pd_policy.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)
-
-const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000,   900, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 10000),
-		PDO_VAR(4750, 21000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
-{
-	struct charge_port_info charge;
-	charge.current = max_ma;
-	charge.voltage = supply_voltage;
-	charge_manager_update_charge(CHARGE_SUPPLIER_PD, port, &charge);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-void typec_set_input_current_limit(int port, uint32_t max_ma,
-				   uint32_t supply_voltage)
-{
-	struct charge_port_info charge;
-	charge.current = max_ma;
-	charge.voltage = supply_voltage;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TYPEC, port, &charge);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_is_valid_input_voltage(int mv)
-{
-	/* Any voltage less than the max is allowed */
-	return 1;
-}
-
-int pd_check_requested_voltage(uint32_t rdo)
-{
-	int max_ma = rdo & 0x3FF;
-	int op_ma = (rdo >> 10) & 0x3FF;
-	int idx = rdo >> 28;
-	uint32_t pdo;
-	uint32_t pdo_ma;
-
-	if (!idx || idx > pd_src_pdo_cnt)
-		return EC_ERROR_INVAL; /* Invalid index */
-
-	/* check current ... */
-	pdo = pd_src_pdo[idx - 1];
-	pdo_ma = (pdo & 0x3ff);
-	if (op_ma > pdo_ma)
-		return EC_ERROR_INVAL; /* too much op current */
-	if (max_ma > pdo_ma)
-		return EC_ERROR_INVAL; /* too much max current */
-
-	CPRINTF("Requested %d V %d mA (for %d/%d mA)\n",
-		((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10,
-		((rdo >> 10) & 0x3ff) * 10, (rdo & 0x3ff) * 10);
-
-	return EC_SUCCESS;
-}
-
-void pd_transition_voltage(int idx)
-{
-	/* No-operation: we are always 5V */
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* provide VBUS */
-	gpio_set_level(GPIO_USBC_5V_EN, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Kill VBUS */
-	gpio_set_level(GPIO_USBC_5V_EN, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return gpio_get_level(GPIO_CHGR_ACOK);
-}
-
-int pd_board_checks(void)
-{
-	return EC_SUCCESS;
-}
-
-int pd_check_power_swap(int port)
-{
-	/* TODO: use battery level to decide to accept/reject power swap */
-	/*
-	 * Allow power swap as long as we are acting as a dual role device,
-	 * otherwise assume our role is fixed (not in S0 or console command
-	 * to fix our role).
-	 */
-	return pd_get_dual_role() == PD_DRP_TOGGLE_ON ? 1 : 0;
-}
-
-int pd_check_data_swap(int port, int data_role)
-{
-	/* Always allow data swap: we can be DFP or UFP for USB */
-	return 1;
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/*
-	 * VCONN is provided directly by the battery(PPVAR_SYS)
-	 * but use the same rules as power swap
-	 */
-	return pd_get_dual_role() == PD_DRP_TOGGLE_ON ? 1 : 0;
-}
-
-void pd_execute_data_swap(int port, int data_role)
-{
-	/* inform the host controller to change role */
-	pd_send_host_event(PD_EVENT_DATA_SWAP);
-}
-
-void pd_check_pr_role(int port, int pr_role, int flags)
-{
-	/*
-	 * If partner is dual-role power and dualrole toggling is on, consider
-	 * if a power swap is necessary.
-	 */
-	if ((flags & PD_FLAGS_PARTNER_DR_POWER) &&
-	    pd_get_dual_role() == PD_DRP_TOGGLE_ON) {
-		/*
-		 * If we are source and partner is externally powered,
-		 * swap to become a sink.
-		 */
-		if ((flags & PD_FLAGS_PARTNER_EXTPOWER) &&
-		    pr_role == PD_ROLE_SOURCE)
-			pd_request_power_swap(port);
-	}
-}
-
-void pd_check_dr_role(int port, int dr_role, int flags)
-{
-	/* if the partner is a DRP (e.g. laptop), try to switch to UFP */
-	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_DFP)
-		pd_request_data_swap(port);
-}
-
-int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
-{
-	return 0;
-}
diff --git a/board/ryu_sh/Makefile b/board/ryu_sh/Makefile
deleted file mode 120000
index 94aaae2c4d..0000000000
--- a/board/ryu_sh/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-../../Makefile
\ No newline at end of file
diff --git a/board/ryu_sh/board.c b/board/ryu_sh/board.c
deleted file mode 100644
index 9df92bb31f..0000000000
--- a/board/ryu_sh/board.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* ryu sensor hub configuration */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accelgyro_lsm6ds0.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SUSPEND,  1, "SUSPEND_ASSERTED"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
-	{"slave",  I2C_PORT_SLAVE, 100,
-		GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Sensor mutex */
-static struct mutex g_mutex;
-
-/*  local sensor data (per-sensor) */
-struct motion_data_t g_saved_data[2];
-
-struct motion_sensor_t motion_sensors[] = {
-
-	/*
-	 * Note: lsm6ds0: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	{.name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LSM6DS0,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &lsm6ds0_drv,
-	 .mutex = &g_mutex,
-	 .drv_data = &g_saved_data[0],
-	 .i2c_addr = LSM6DS0_ADDR1,
-	 .rot_standard_ref = NULL,
-	 .default_config = {
-		 .odr = 119000,
-		 .range = 2,
-		 .ec_rate = SUSPEND_SAMPLING_INTERVAL,
-	 }
-	},
-
-	{.name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LSM6DS0,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &lsm6ds0_drv,
-	 .mutex = &g_mutex,
-	 .drv_data = &g_saved_data[1],
-	 .i2c_addr = LSM6DS0_ADDR1,
-	 .rot_standard_ref = NULL,
-	 .default_config = {
-		 .odr = 119000,
-		 .range = 2000,
-		 .ec_rate = SUSPEND_SAMPLING_INTERVAL,
-	 }
-	},
-
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/*
- * Note: If a new sensor driver is added, make sure to update the following
- * assert.
- */
-BUILD_ASSERT(ARRAY_SIZE(motion_sensors) == ARRAY_SIZE(g_saved_data));
-
-void board_config_pre_init(void)
-{
-	/*
-	 *  enable SYSCFG clock:
-	 *  otherwise the SYSCFG peripheral is not clocked during the pre-init
-	 *  and the register write as no effect.
-	 */
-	STM32_RCC_APB2ENR |= 1 << 0;
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-	/*
-	 * Remap USART DMA to match the USART driver
-	 * the DMA mapping is :
-	 *  Chan 4 : USART1_TX
-	 *  Chan 5 : USART1_RX
-	 */
-	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
-}
diff --git a/board/ryu_sh/board.h b/board/ryu_sh/board.h
deleted file mode 100644
index 67bafb3693..0000000000
--- a/board/ryu_sh/board.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ryu sensor board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART1 (PA9/PA10) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-
-/*
- * The RO firmware image size is limited to 40K to
- * leave more space to the RW image.
- */
-#undef CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_IMAGE_SIZE (40*1024)
-#undef CONFIG_FW_INCLUDE_RO
-
-/* By default, enable all console messages  */
-#define CC_DEFAULT     CC_ALL
-
-/* Optional features */
-#undef CONFIG_EXTPOWER
-#undef CONFIG_HIBERNATE
-#define CONFIG_ACCELGYRO_LSM6DS0
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_I2C
-#define CONFIG_BOARD_PRE_INIT
-#undef  CONFIG_LID_SWITCH
-#undef CONFIG_CMD_POWER_AP
-#define CONFIG_POWER_COMMON
-#define CONFIG_CHIPSET_ECDRIVEN
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_VBOOT_HASH
-#undef CONFIG_WATCHDOG_HELP
-
-/* I2C ports configuration */
-#define I2C_PORT_MASTER 1
-#define I2C_PORT_SLAVE  0
-#define I2C_PORT_EC I2C_PORT_SLAVE
-#define I2C_PORT_ACCEL I2C_PORT_MASTER
-#define I2C_PORT_COMPASS I2C_PORT_MASTER
-
-/* slave address for host commands */
-#ifdef HAS_TASK_HOSTCMD
-#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR 0x3e
-#endif
-
-/*
- * Write protect is active high, but given WP line is not implemented,
- * the memory is not write protected.
- */
-#define CONFIG_WP_ACTIVE_HIGH
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-#include "gpio_signal.h"
-
-enum power_signal {
-	ECDRIVEN_SUSPEND_ASSERTED,
-
-	/* Number of power signals */
-	POWER_SIGNAL_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/ryu_sh/build.mk b/board/ryu_sh/build.mk
deleted file mode 100644
index b89b8f40b3..0000000000
--- a/board/ryu_sh/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072VBH6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o
-
-# This target builds RW only.  Therefore, remove RO from dependencies.
-all_deps=$(patsubst ro,,$(def_all_deps))
diff --git a/board/ryu_sh/ec.tasklist b/board/ryu_sh/ec.tasklist
deleted file mode 100644
index 421cf57ed8..0000000000
--- a/board/ryu_sh/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * List of enabled tasks in the priority order
- *
- * The first one has the lowest priority.
- *
- * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
- * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
- * where :
- * 'n' in the name of the task
- * 'r' in the main routine of the task
- * 'd' in an opaque parameter passed to the routine at startup
- * 's' is the stack size in bytes; must be a multiple of 8
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
diff --git a/board/ryu_sh/gpio.inc b/board/ryu_sh/gpio.inc
deleted file mode 100644
index 772309018a..0000000000
--- a/board/ryu_sh/gpio.inc
+++ /dev/null
@@ -1,47 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupts */
-GPIO_INT(AP_IN_SUSPEND,    PIN(E, 9),  GPIO_INT_BOTH,       power_signal_interrupt)
-/*
- * TODO(gwendal): Follow Rambus work.
- * Combined accelerometer input. This will become an interrupt, once we have
- * support for it.
- */
-GPIO(ACC_IRQ,              PIN(B, 12), GPIO_INPUT)
-
-/* Outputs */
-GPIO(SH_EC_SIGNAL,         PIN(A, 7),  GPIO_OUT_LOW)
-GPIO(SH_IRQ_L,             PIN(A, 11), GPIO_OUT_LOW)
-
-/* Inputs */
-GPIO(LID_CLOSED,           PIN(A,  2), GPIO_INPUT)
-GPIO(BASE_PRESENT,         PIN(A,  3), GPIO_INPUT)
-GPIO(COMPASS_DRDY,         PIN(B, 11), GPIO_INPUT)
-
-#if 0
-/* Alternate functions */
-GPIO(UART_TX,              PIN(A,  9), GPIO_OUT_LOW)
-GPIO(UART_RX,              PIN(A, 10), GPIO_OUT_LOW)
-#endif
-
-/* Needed to bypass flash write protection */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(SLAVE_I2C_SCL,        PIN(B,  6), GPIO_INPUT)
-GPIO(SLAVE_I2C_SDA,        PIN(B,  7), GPIO_INPUT)
-GPIO(MASTER_I2C_SCL,       PIN(B, 13), GPIO_INPUT)
-GPIO(MASTER_I2C_SDA,       PIN(B, 14), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,   0) /* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(B, 0x00C0), 1, MODULE_I2C,    0) /* I2C SLAVE:PB6/7 */
-ALTERNATE(PIN_MASK(B, 0x6000), 5, MODULE_I2C,    0) /* I2C MASTER:PB13/14 */
diff --git a/board/ryu_sh_loader/Makefile b/board/ryu_sh_loader/Makefile
deleted file mode 120000
index 94aaae2c4d..0000000000
--- a/board/ryu_sh_loader/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-../../Makefile
\ No newline at end of file
diff --git a/board/ryu_sh_loader/board.c b/board/ryu_sh_loader/board.c
deleted file mode 100644
index 80071612c5..0000000000
--- a/board/ryu_sh_loader/board.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* ryu sensor hub configuration */
-
-#include "common.h"
-#include "console.h"
-#include "driver/accelgyro_lsm6ds0.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"slave",  I2C_PORT_SLAVE, 100,
-		GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-void board_config_pre_init(void)
-{
-	/*
-	 *  enable SYSCFG clock:
-	 *  otherwise the SYSCFG peripheral is not clocked during the pre-init
-	 *  and the register write as no effect.
-	 */
-	STM32_RCC_APB2ENR |= 1 << 0;
-	/*
-	 * Remap USART DMA to match the USART driver
-	 * the DMA mapping is :
-	 *  Chan 4 : USART1_TX
-	 *  Chan 5 : USART1_RX
-	 */
-	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
-}
diff --git a/board/ryu_sh_loader/board.h b/board/ryu_sh_loader/board.h
deleted file mode 100644
index 0453332da7..0000000000
--- a/board/ryu_sh_loader/board.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ryu sensor board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART1 (PA9/PA10) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-
-/*
- * The firmware image size is limited to 40K to
- * leave more space to the RW image.
- */
-#undef CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_IMAGE_SIZE (40*1024)
-
-/* By default, enable all console messages  */
-#define CC_DEFAULT     CC_ALL
-
-/* Optional features */
-#undef CONFIG_EXTPOWER
-#undef CONFIG_HIBERNATE
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_I2C
-#define CONFIG_BOARD_PRE_INIT
-#undef  CONFIG_LID_SWITCH
-#undef CONFIG_CMD_POWER_AP
-#define CONFIG_POWER_COMMON
-#define CONFIG_VBOOT_HASH
-#undef CONFIG_WATCHDOG_HELP
-
-/* I2C ports configuration */
-#define I2C_PORT_SLAVE  0
-#define I2C_PORT_EC I2C_PORT_SLAVE
-
-/* slave address for host commands */
-#ifdef HAS_TASK_HOSTCMD
-#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR 0x3e
-#endif
-
-/*
- * Write protect is active high, but given WP line is not implemented,
- * the memory is not write protected.
- */
-#define CONFIG_WP_ACTIVE_HIGH
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/ryu_sh_loader/build.mk b/board/ryu_sh_loader/build.mk
deleted file mode 100644
index 76ac52f9e5..0000000000
--- a/board/ryu_sh_loader/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072VBH6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o
diff --git a/board/ryu_sh_loader/ec.tasklist b/board/ryu_sh_loader/ec.tasklist
deleted file mode 100644
index aaed7865c8..0000000000
--- a/board/ryu_sh_loader/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * List of enabled tasks in the priority order
- *
- * The first one has the lowest priority.
- *
- * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
- * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
- * where :
- * 'n' in the name of the task
- * 'r' in the main routine of the task
- * 'd' in an opaque parameter passed to the routine at startup
- * 's' is the stack size in bytes; must be a multiple of 8
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
diff --git a/board/ryu_sh_loader/gpio.inc b/board/ryu_sh_loader/gpio.inc
deleted file mode 100644
index 52565b3fa1..0000000000
--- a/board/ryu_sh_loader/gpio.inc
+++ /dev/null
@@ -1,37 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupts */
-GPIO_INT(AP_IN_SUSPEND,        PIN(E, 9),  GPIO_INT_BOTH,                   power_signal_interrupt)
-
-/* Outputs */
-GPIO(SH_EC_SIGNAL,         PIN(A, 7),  GPIO_OUT_LOW)
-GPIO(SH_IRQ_L,             PIN(A, 11), GPIO_OUT_LOW)
-
-/* Inputs */
-GPIO(LID_CLOSED,           PIN(A,  2), GPIO_INPUT)
-GPIO(BASE_PRESENT,         PIN(A,  3), GPIO_INPUT)
-
-#if 0
-/* Alternate functions */
-GPIO(UART_TX,              PIN(A,  9), GPIO_OUT_LOW)
-GPIO(UART_RX,              PIN(A, 10), GPIO_OUT_LOW)
-#endif
-
-/* Needed to bypass flash write protection */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(SLAVE_I2C_SCL,        PIN(B,  6), GPIO_INPUT)
-GPIO(SLAVE_I2C_SDA,        PIN(B,  7), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,   0) /* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(B, 0x00C0), 1, MODULE_I2C,    0) /* I2C SLAVE:PB6/7 */
diff --git a/util/flash_ec b/util/flash_ec
index b94ed556d9..9f93de66b2 100755
--- a/util/flash_ec
+++ b/util/flash_ec
@@ -70,8 +70,6 @@ BOARDS_STM32=(
 	pit
 	plankton
 	ryu
-	ryu_p4p5
-	ryu_sh
 	samus_pd
 	strago_pd
 	zinger
@@ -264,7 +262,6 @@ function ec_uart() {
 
 # Servo variables management
 case "${BOARD}" in
-	ryu_sh ) MCU="sh" ;;
 	glados_pd|oak_pd|samus_pd ) MCU="usbpd" ;;
 	kunimitsu_pd|strago_pd ) MCU="usbpd" ;;
 	dingdong|hoho|twinkie ) DUT_CONTROL_CMD="true" ; MCU="ec" ;;