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| author | Tinghan Shen <tinghan.shen@mediatek.com> | 2021-10-28 17:43:43 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-10-29 09:48:44 +0000 |
| commit | b2febc1af2da88b5f38f1b8b7c0b27925e2b2f4e (patch) | |
| tree | ea62cb9fbd34dcbbaf334e10357b22a2bcaaaccd | |
| parent | fa2a95c0938617cb1ec4657bb8a3b307578ffe2a (diff) | |
| download | chrome-ec-b2febc1af2da88b5f38f1b8b7c0b27925e2b2f4e.tar.gz | |
chip/mt_scp: dump 8195 panic information on console channel
Save the panic information on DRAM to keep it available at next reboot.
This requires a new non-cacheable DRAM MPU with RW permission.
Besides panic information, also checks the WDT latch registers that will
latch PC/SP/LR when triggered SCP WDT timeout.
BRANCH=None
BUG=b:199444513
BUG=b:189356151
TEST=see exception log at /var/log/cros_scp.log on tomato board
Change-Id: Ief9db8ec8b5b83805c21370d6be8ff49a8bb98df
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3250076
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
| -rw-r--r-- | baseboard/mtscp-rv32i/baseboard.c | 25 | ||||
| -rw-r--r-- | baseboard/mtscp-rv32i/baseboard.h | 11 | ||||
| -rw-r--r-- | chip/mt_scp/rv32i_common/registers.h | 3 |
3 files changed, 39 insertions, 0 deletions
diff --git a/baseboard/mtscp-rv32i/baseboard.c b/baseboard/mtscp-rv32i/baseboard.c index a34a08f1fe..ac261c3aa8 100644 --- a/baseboard/mtscp-rv32i/baseboard.c +++ b/baseboard/mtscp-rv32i/baseboard.c @@ -6,6 +6,7 @@ #include "cache.h" #include "csr.h" +#include "hooks.h" #include "registers.h" #define SCP_SRAM_END (CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) @@ -25,9 +26,33 @@ struct mpu_entry mpu_entries[NR_MPU_ENTRIES] = { {0x70000000, 0x80000000, MPU_ATTR_W | MPU_ATTR_R}, #ifdef CHIP_VARIANT_MT8195 {0x10000000, 0x11400000, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R}, + {CONFIG_PANIC_DRAM_BASE, CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_DRAM_SIZE, MPU_ATTR_W | MPU_ATTR_R}, #else {0x10000000, 0x11400000, MPU_ATTR_W | MPU_ATTR_R}, #endif }; #include "gpio_list.h" + +#ifdef CONFIG_PANIC_CONSOLE_OUTPUT +static void report_previous_panic(void) +{ + struct panic_data * panic = panic_get_data(); + + if (panic == NULL && SCP_CORE0_MON_PC_LATCH == 0) + return; + + ccprintf("[Previous Panic]\n"); + if (panic) { + panic_data_ccprint(panic); + } else { + ccprintf("No panic data\n"); + } + ccprintf("Latch PC:%x LR:%x SP:%x\n", + SCP_CORE0_MON_PC_LATCH, + SCP_CORE0_MON_LR_LATCH, + SCP_CORE0_MON_SP_LATCH); + +} +DECLARE_HOOK(HOOK_INIT, report_previous_panic, HOOK_PRIO_DEFAULT); +#endif diff --git a/baseboard/mtscp-rv32i/baseboard.h b/baseboard/mtscp-rv32i/baseboard.h index a8f3b522a0..d7694cd1c7 100644 --- a/baseboard/mtscp-rv32i/baseboard.h +++ b/baseboard/mtscp-rv32i/baseboard.h @@ -15,6 +15,10 @@ #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE #define CONFIG_UART_CONSOLE 0 +#ifdef CHIP_VARIANT_MT8195 +#define CONFIG_PANIC_CONSOLE_OUTPUT +#endif + /* IPI configs */ #define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288 #define CONFIG_IPC_SHARED_OBJ_ADDR \ @@ -51,6 +55,13 @@ #define CONFIG_DRAM_BASE_LOAD 0x50000000 #define CONFIG_DRAM_SIZE 0x01400000 /* 20 MB */ +/* Add some space (0x100) before panic for jump data */ +#define CONFIG_PANIC_DRAM_BASE (CONFIG_DRAM_BASE + CONFIG_DRAM_SIZE) +#define CONFIG_PANIC_DRAM_SIZE 0x00001000 /* 4K */ + +#define CONFIG_PANIC_BASE_OFFSET 0x100 /* reserved for jump data */ +#define CONFIG_PANIC_DATA_BASE (CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_BASE_OFFSET) + /* MPU settings */ #define NR_MPU_ENTRIES 16 diff --git a/chip/mt_scp/rv32i_common/registers.h b/chip/mt_scp/rv32i_common/registers.h index adbef5f98b..afe706948e 100644 --- a/chip/mt_scp/rv32i_common/registers.h +++ b/chip/mt_scp/rv32i_common/registers.h @@ -140,6 +140,9 @@ #define WDT_EN BIT(31) #define SCP_CORE0_WDT_KICK REG32(SCP_REG_BASE + 0x30038) #define SCP_CORE0_WDT_CUR_VAL REG32(SCP_REG_BASE + 0x3003C) +#define SCP_CORE0_MON_PC_LATCH REG32(SCP_REG_BASE + 0x300D0) +#define SCP_CORE0_MON_LR_LATCH REG32(SCP_REG_BASE + 0x300D4) +#define SCP_CORE0_MON_SP_LATCH REG32(SCP_REG_BASE + 0x300D8) /* INTC */ #define SCP_INTC_WORD(irq) ((irq) >> 5) /* word length = 2^5 */ |