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| author | Keith Short <keithshort@chromium.org> | 2021-01-07 17:25:30 +0000 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-01-07 20:14:05 +0000 |
| commit | c1850a39b02cfcb7ff45282078ad606bc3526649 (patch) | |
| tree | 60ce42607fde2ac0e1815b2254d1308a53617c1b | |
| parent | 351a96788785a3d83b9303f7f4b5c22c9b7ac3a7 (diff) | |
| download | chrome-ec-c1850a39b02cfcb7ff45282078ad606bc3526649.tar.gz | |
Revert "TCPMv2: Decrease Low Power Mode debounce delay to 10 ms"
This reverts commit 5ff18dfd6ab67df2e62c6af9f20ed472808de707.
Reason for revert: b:176986511 Volteer family devices need at least
75ms debounce to detect attachment of SNK devices.
Original change's description:
> TCPMv2: Decrease Low Power Mode debounce delay to 10 ms
>
> This patch decreases PD_LPM_DEBOUNCE to 10 ms. With current
> 100 ms delay ANX7447 can't go to Low Power Mode due to silicon
> bug (b:77544959). When DRP mode is enabled ANX7447 triggers alert
> every 39.7 ms. Checking what caused an alert involves I2C
> transaction which changes timeout after which TCPC goes to Low
> Power Mode to get_time().val + PD_LPM_DEBOUNCE_US. As a result it
> is not possible to put TCPC to LPM which is necessary to work
> properly (b:149761477)
>
> Original value for PD_LPM_DEBOUNCE_US was 10 ms, introduced
> in CL:1119255. This value is still used in TCPMv1.
> For TCPMv2, PD_LPM_DEBOUNCE_US was changed to 100 ms in CL:2126078.
> It is unclear why this value was changed. Review discussion and bug
> b:149772936 don't mention why we needed to change that, so we change
> it back to 10 ms for consistency with TCPMv1.
>
> Issue was found when running EC ToT with TCPMv2 enabled on bobba board.
>
> BUG=b:161775827, b:77544959, b:149761477
> BRANCH=none
> TEST=Flash EC ToT on octopus board with ANX7447 (eg. bobba).
> Make sure that DRP mode is enabled. Connect charger to port
> with ANX7447 chip. Make sure that EC can connect with charger.
>
> Signed-off-by: Patryk Duda <pdk@semihalf.com>
> Change-Id: Ia08818378a1fca424d392b4699f9c4adc460bfb5
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606235
> Reviewed-by: Edward Hill <ecgh@chromium.org>
Bug: b:161775827
Bug: b:77544959
Bug: b:149761477
Change-Id: I882c077915b67b53acc73e2941ead33baabe9b5f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2615118
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Tested-by: Keith Short <keithshort@chromium.org>
| -rw-r--r-- | common/usbc/usb_tc_drp_acc_trysrc_sm.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/common/usbc/usb_tc_drp_acc_trysrc_sm.c b/common/usbc/usb_tc_drp_acc_trysrc_sm.c index 9999fa6627..1df7710301 100644 --- a/common/usbc/usb_tc_drp_acc_trysrc_sm.c +++ b/common/usbc/usb_tc_drp_acc_trysrc_sm.c @@ -123,13 +123,8 @@ void print_flag(int port, int set_or_clear, int flag); #define CLR_ALL_BUT_LPM_FLAGS(port) TC_CLR_FLAG(port, \ ~(TC_FLAGS_LPM_ENGAGED | TC_FLAGS_SUSPEND)) -/* - * 10 ms is enough time for any TCPC transaction to complete - * - * This value must be below ~39.7 ms to put ANX7447 into LPM due to bug in - * silicon (see b/77544959 and b/149761477 for more details). - */ -#define PD_LPM_DEBOUNCE_US (10 * MSEC) +/* 100 ms is enough time for any TCPC transaction to complete. */ +#define PD_LPM_DEBOUNCE_US (100 * MSEC) /* * This delay is not part of the USB Type-C specification or the USB port |