diff options
| author | Alec Berg <alecaberg@chromium.org> | 2015-10-19 10:04:23 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-10-19 15:15:36 -0700 |
| commit | cb3e0ca7865d920bd89997046641b48c040e2a36 (patch) | |
| tree | eff0f0443249ffd29cf881baebaa8886b5661500 | |
| parent | 8acea1ec3970fe5b829d2b06ba32529c9d5ccb6a (diff) | |
| download | chrome-ec-cb3e0ca7865d920bd89997046641b48c040e2a36.tar.gz | |
stm32f05x: Use correct erase block size of 1kB
Change erase block size to the correct 1kB.
BUG=chrome-os-partner:41959
BRANCH=none
TEST=with following CL, test software sync to PD MCU on
glados.
Change-Id: I6252e6344e50f00249ab105a90febd15599c936f
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/307042
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
| -rw-r--r-- | chip/stm32/config-stm32f05x.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h index 648347879a..cab7b62d50 100644 --- a/chip/stm32/config-stm32f05x.h +++ b/chip/stm32/config-stm32f05x.h @@ -6,7 +6,7 @@ /* Memory mapping */ #define CONFIG_FLASH_SIZE (64 * 1024) #define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ +#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ /* No page mode on STM32F, so no benefit to larger write sizes */ |