npcx: add GPIO support for npcx9 and refactor GPIO driver

1. Add GPIO driver support for npcx9.
2. move the GPIO interrupt handler (MIWU) from gpio.h to gpio-npcx5.h,
gpio-npcx7.h, and gpio-npcx9.h separately.
Note: gpio-npcx7.h is a link to gpio-npcx5.h because almost all of the
source codes are the same.

BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST=with related CLs, build and flash image on the npcx5/7/9 EVB and
yorp; verify GPIO functionality.

Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I665507f804ca3772f81f0ff8bd917a633bda2d11
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402842
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>

8 files changed, 899 insertions, 185 deletions

diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk
index f33089bc60..61137f5856 100644
--- a/chip/npcx/build.mk
+++ b/chip/npcx/build.mk
@@ -19,6 +19,7 @@ endif
 # Required chip modules
 chip-y=header.o clock.o gpio.o hwtimer.o system.o uart.o uartn.o sib.o
 chip-y+=system-$(CHIP_FAMILY).o
+chip-y+=gpio-$(CHIP_FAMILY).o
 
 # Optional chip modules
 chip-$(CONFIG_ADC)+=adc.o
diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c
new file mode 100644
index 0000000000..d6a28300ba
--- /dev/null
+++ b/chip/npcx/gpio-npcx5.c
@@ -0,0 +1,198 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* GPIO module for Chrome EC */
+
+#include "clock.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "gpio_chip.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lpc_chip.h"
+#include "registers.h"
+#include "task.h"
+
+/*
+ * List of GPIO IRQs to enable. Don't automatically enable interrupts for
+ * the keyboard input GPIO bank - that's handled separately. Of course the
+ * bank is different for different systems.
+ */
+static void gpio_init(void)
+{
+	/* Enable IRQs now that pins are set up */
+	task_enable_irq(NPCX_IRQ_MTC_WKINTAD_0);
+	task_enable_irq(NPCX_IRQ_WKINTEFGH_0);
+	task_enable_irq(NPCX_IRQ_WKINTC_0);
+	task_enable_irq(NPCX_IRQ_TWD_WKINTB_0);
+	task_enable_irq(NPCX_IRQ_WKINTA_1);
+	task_enable_irq(NPCX_IRQ_WKINTB_1);
+#ifndef HAS_TASK_KEYSCAN
+	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
+#endif
+	task_enable_irq(NPCX_IRQ_WKINTD_1);
+	task_enable_irq(NPCX_IRQ_WKINTE_1);
+	task_enable_irq(NPCX_IRQ_WKINTF_1);
+	task_enable_irq(NPCX_IRQ_WKINTG_1);
+	task_enable_irq(NPCX_IRQ_WKINTH_1);
+#if defined(CHIP_FAMILY_NPCX7)
+	task_enable_irq(NPCX_IRQ_WKINTFG_2);
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
+
+/**
+ * Handlers for each GPIO port.  These read and clear the interrupt bits for
+ * the port, then call the master handler above.
+ */
+
+#define GPIO_IRQ_FUNC(_irq_func, wui_int)		\
+void _irq_func(void)					\
+{							\
+	gpio_interrupt(wui_int);			\
+}
+
+/* If we need to handle the other type interrupts except GPIO, add code here */
+void __gpio_wk0efgh_interrupt(void)
+{
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		/* Pending bit 7 or 6 or 5? */
+		if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) &&
+			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
+			/* Disable host wake-up */
+			CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
+			/* Clear pending bit of WUI */
+			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
+			return;
+		}
+		if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
+				&&
+			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
+				espi_espirst_handler();
+				return;
+			}
+		} else {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7)
+				&&
+			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) {
+				lpc_lreset_pltrst_handler();
+				return;
+			}
+		}
+	}
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_5));
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_6));
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_7));
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_8));
+}
+
+#ifdef CONFIG_HOSTCMD_RTC
+static void set_rtc_host_event(void)
+{
+	host_set_single_event(EC_HOST_EVENT_RTC);
+}
+DECLARE_DEFERRED(set_rtc_host_event);
+#endif
+
+void __gpio_rtc_interrupt(void)
+{
+	/* Check pending bit 7 */
+#ifdef CONFIG_HOSTCMD_RTC
+	if (NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_4) & 0x80) {
+		/* Clear pending bit for WUI */
+		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_4), 7);
+		hook_call_deferred(&set_rtc_host_event_data, 0);
+		return;
+	}
+#endif
+#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
+	(CONFIG_CONSOLE_UART == 1)
+	/* Handle the interrupt from UART wakeup event */
+	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6) &&
+	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_1), 6)) {
+		/*
+		 * Disable WKEN bit to avoid the other unnecessary interrupts
+		 * from the coming data bits after the start bit. (Pending bit
+		 * of CR_SIN is set when a high-to-low transaction occurs.)
+		 */
+		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6);
+		/* Clear pending bit for WUI */
+		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_1), 6);
+		/* Notify the clock module that the console is in use. */
+		clock_refresh_console_in_use();
+		return;
+	}
+#endif
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1));
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4));
+}
+
+void __gpio_wk1h_interrupt(void)
+{
+#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
+	(CONFIG_CONSOLE_UART == 0)
+	/* Handle the interrupt from UART wakeup event */
+	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7) &&
+	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_1, MIWU_GROUP_8), 7)) {
+		/*
+		 * Disable WKEN bit to avoid the other unnecessary interrupts
+		 * from the coming data bits after the start bit. (Pending bit
+		 * of CR_SIN is set when a high-to-low transaction occurs.)
+		 */
+		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7);
+		/* Clear pending bit for WUI */
+		SET_BIT(NPCX_WKPCL(MIWU_TABLE_1, MIWU_GROUP_8), 7);
+		/* Notify the clock module that the console is in use. */
+		clock_refresh_console_in_use();
+	} else
+#endif
+		gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8));
+}
+
+GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2));
+GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3));
+GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1));
+GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2));
+#ifndef HAS_TASK_KEYSCAN
+/* Declare GPIO irq functions for KSI pins if there's no keyboard scan task, */
+GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3));
+#endif
+GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4));
+GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5));
+GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6));
+GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7));
+#if defined(CHIP_FAMILY_NPCX7)
+GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
+#endif
+
+DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,  __gpio_wk0b_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTC_0,      __gpio_wk0c_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0,   __gpio_wk0efgh_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTA_1,      __gpio_wk1a_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTB_1,      __gpio_wk1b_interrupt, 3);
+#ifndef HAS_TASK_KEYSCAN
+DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,  __gpio_wk1c_interrupt, 3);
+#endif
+DECLARE_IRQ(NPCX_IRQ_WKINTD_1,      __gpio_wk1d_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTE_1,      __gpio_wk1e_interrupt, 3);
+#ifdef CONFIG_HOSTCMD_SPS
+/*
+ * HACK: Make CS GPIO P2 to improve SHI reliability.
+ * TODO: Increase CS-assertion-to-transaction-start delay on host to
+ * accommodate P3 CS interrupt.
+ */
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 2);
+#else
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 3);
+#endif
+DECLARE_IRQ(NPCX_IRQ_WKINTG_1,      __gpio_wk1g_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTH_1,      __gpio_wk1h_interrupt, 3);
+#if defined(CHIP_FAMILY_NPCX7)
+DECLARE_IRQ(NPCX_IRQ_WKINTFG_2,     __gpio_wk2fg_interrupt, 3);
+#endif
+
+#undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/gpio-npcx7.c b/chip/npcx/gpio-npcx7.c
new file mode 120000
index 0000000000..39b939f44c
--- /dev/null
+++ b/chip/npcx/gpio-npcx7.c
@@ -0,0 +1 @@
+gpio-npcx5.c
\ No newline at end of file
diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c
new file mode 100644
index 0000000000..441924d89e
--- /dev/null
+++ b/chip/npcx/gpio-npcx9.c
@@ -0,0 +1,213 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* GPIO module for Chrome EC */
+
+#include "clock.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "gpio_chip.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lct_chip.h"
+#include "lpc_chip.h"
+#include "registers.h"
+#include "task.h"
+
+/*
+ * List of GPIO IRQs to enable. Don't automatically enable interrupts for
+ * the keyboard input GPIO bank - that's handled separately. Of course the
+ * bank is different for different systems.
+ */
+static void gpio_init(void)
+{
+	/* Enable IRQs now that pins are set up */
+	task_enable_irq(NPCX_IRQ_CR_SIN2_WKINTA_0);
+	task_enable_irq(NPCX_IRQ_TWD_WKINTB_0);
+	task_enable_irq(NPCX_IRQ_WKINTC_0);
+	task_enable_irq(NPCX_IRQ_MTC_WKINTD_0);
+	task_enable_irq(NPCX_IRQ_WKINTE_0);
+	task_enable_irq(NPCX_IRQ_WKINTF_0);
+	task_enable_irq(NPCX_IRQ_WKINTG_0);
+	task_enable_irq(NPCX_IRQ_WKINTH_0);
+	task_enable_irq(NPCX_IRQ_WKINTA_1);
+	task_enable_irq(NPCX_IRQ_WKINTB_1);
+#ifndef HAS_TASK_KEYSCAN
+	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
+#endif
+	task_enable_irq(NPCX_IRQ_WKINTD_1);
+	task_enable_irq(NPCX_IRQ_WKINTE_1);
+	task_enable_irq(NPCX_IRQ_WKINTF_1);
+	task_enable_irq(NPCX_IRQ_WKINTG_1);
+	task_enable_irq(NPCX_IRQ_WKINTH_1);
+	task_enable_irq(NPCX_IRQ_LCT_WKINTF_2);
+}
+DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
+
+/**
+ * Handlers for each GPIO port.  These read and clear the interrupt bits for
+ * the port, then call the master handler above.
+ */
+
+#define GPIO_IRQ_FUNC(_irq_func, wui_int)		\
+void _irq_func(void)					\
+{							\
+	gpio_interrupt(wui_int);			\
+}
+
+/* If we need to handle the other type interrupts except GPIO, add code here */
+void __gpio_host_interrupt(void)
+{
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		/* Pending bit 7 or 6 or 5? */
+		if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) &&
+			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
+			/* Disable host wake-up */
+			CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
+			/* Clear pending bit of WUI */
+			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
+			return;
+		}
+		if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
+					&&
+			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
+				espi_espirst_handler();
+				return;
+			}
+		} else {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7)
+					&&
+			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) {
+				lpc_lreset_pltrst_handler();
+				return;
+			}
+		}
+	}
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_5));
+}
+
+#ifdef CONFIG_HOSTCMD_RTC
+static void set_rtc_host_event(void)
+{
+	host_set_single_event(EC_HOST_EVENT_RTC);
+}
+DECLARE_DEFERRED(set_rtc_host_event);
+#endif
+
+void __gpio_rtc_interrupt(void)
+{
+	/* Check pending bit 7 */
+#ifdef CONFIG_HOSTCMD_RTC
+	if (NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_4) & 0x80) {
+		/* Clear pending bit for WUI */
+		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_4), 7);
+		hook_call_deferred(&set_rtc_host_event_data, 0);
+		return;
+	}
+#endif
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4));
+}
+void __gpio_cr_sin2_interrupt(void)
+{
+#if defined(CONFIG_LOW_POWER_IDLE) && (CONFIG_CONSOLE_UART == 1)
+	/* Handle the interrupt from UART wakeup event */
+	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6) &&
+	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_1), 6)) {
+		/*
+		 * Disable WKEN bit to avoid the other unnecessary interrupts
+		 * from the coming data bits after the start bit. (Pending bit
+		 * of CR_SIN is set when a high-to-low transaction occurs.)
+		 */
+		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6);
+		/* Clear pending bit for WUI */
+		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_1), 6);
+		/* Notify the clock module that the console is in use. */
+		clock_refresh_console_in_use();
+		return;
+	}
+#endif
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1));
+
+}
+
+void __gpio_wk1h_interrupt(void)
+{
+#if defined(CONFIG_LOW_POWER_IDLE) && (CONFIG_CONSOLE_UART == 0)
+	/* Handle the interrupt from UART wakeup event */
+	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7) &&
+	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_1, MIWU_GROUP_8), 7)) {
+		/*
+		 * Disable WKEN bit to avoid the other unnecessary interrupts
+		 * from the coming data bits after the start bit. (Pending bit
+		 * of CR_SIN is set when a high-to-low transaction occurs.)
+		 */
+		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7);
+		/* Clear pending bit for WUI */
+		SET_BIT(NPCX_WKPCL(MIWU_TABLE_1, MIWU_GROUP_8), 7);
+		/* Notify the clock module that the console is in use. */
+		clock_refresh_console_in_use();
+	} else
+#endif
+		gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8));
+}
+
+void __gpio_lct_interrupt(void)
+{
+	if (NPCX_WKPND(MIWU_TABLE_2, MIWU_GROUP_6) & LCT_WUI_MASK) {
+		NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_6) |= LCT_WUI_MASK;
+		npcx_lct_clear_event();
+		return;
+	}
+	gpio_interrupt(WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
+}
+
+GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2));
+GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3));
+GPIO_IRQ_FUNC(__gpio_wk0f_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_6));
+GPIO_IRQ_FUNC(__gpio_wk0g_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_7));
+GPIO_IRQ_FUNC(__gpio_wk0h_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_8));
+GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1));
+GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2));
+#ifndef HAS_TASK_KEYSCAN
+/* Declare GPIO irq functions for KSI pins if there's no keyboard scan task, */
+GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3));
+#endif
+GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4));
+GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5));
+GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6));
+GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7));
+GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
+
+DECLARE_IRQ(NPCX_IRQ_CR_SIN2_WKINTA_0, __gpio_cr_sin2_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,     __gpio_wk0b_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTC_0,         __gpio_wk0c_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0,     __gpio_rtc_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTE_0,         __gpio_host_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTF_0,         __gpio_wk0f_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTG_0,         __gpio_wk0g_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTH_0,         __gpio_wk0h_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTA_1,         __gpio_wk1a_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTB_1,         __gpio_wk1b_interrupt, 3);
+#ifndef HAS_TASK_KEYSCAN
+DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,     __gpio_wk1c_interrupt, 3);
+#endif
+DECLARE_IRQ(NPCX_IRQ_WKINTD_1,         __gpio_wk1d_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTE_1,         __gpio_wk1e_interrupt, 3);
+#ifdef CONFIG_HOSTCMD_SPS
+/*
+ * HACK: Make CS GPIO P2 to improve SHI reliability.
+ * TODO: Increase CS-assertion-to-transaction-start delay on host to
+ * accommodate P3 CS interrupt.
+ */
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1,         __gpio_wk1f_interrupt, 2);
+#else
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1,         __gpio_wk1f_interrupt, 3);
+#endif
+DECLARE_IRQ(NPCX_IRQ_WKINTG_1,         __gpio_wk1g_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTH_1,         __gpio_wk1h_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_LCT_WKINTF_2,     __gpio_lct_interrupt, 3);
+
+#undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c
index d24525bad1..75c8142d63 100644
--- a/chip/npcx/gpio.c
+++ b/chip/npcx/gpio.c
@@ -5,21 +5,17 @@
 
 /* GPIO module for Chrome EC */
 
-#include "clock.h"
 #include "common.h"
 #include "gpio.h"
 #include "gpio_chip.h"
 #include "i2c.h"
-#include "keyboard_config.h"
 #include "hooks.h"
 #include "registers.h"
-#include "switch.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
 #include "system.h"
 #include "system_chip.h"
-#include "lpc_chip.h"
 #include "ec_commands.h"
 #include "host_command.h"
 #include "hwtimer_chip.h"
@@ -55,18 +51,31 @@ struct npcx_gpio {
 
 BUILD_ASSERT(sizeof(struct npcx_gpio) == 1);
 
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+struct npcx_alt {
+	uint8_t group;
+	uint8_t bit       : 3;
+	uint8_t inverted  : 1;
+	uint8_t reserved  : 4;
+};
+#else
 struct npcx_alt {
 	uint8_t group     : 4;
 	uint8_t bit       : 3;
 	uint8_t inverted  : 1;
 };
+#endif
 
 struct gpio_alt_map {
 	struct npcx_gpio gpio;
 	struct npcx_alt  alt;
 };
 
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+BUILD_ASSERT(sizeof(struct gpio_alt_map) == 3);
+#else
 BUILD_ASSERT(sizeof(struct gpio_alt_map) == 2);
+#endif
 
 /* Constants for GPIO alternative mapping */
 const struct gpio_alt_map gpio_alt_table[] = NPCX_ALT_TABLE;
@@ -378,7 +387,7 @@ int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
 void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 {
 	/* If all GPIO pins are locked, return directly */
-#if defined(CHIP_FAMILY_NPCX7)
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	if ((NPCX_PLOCK_CTL(port) & mask) == mask)
 		return;
 #endif
@@ -447,7 +456,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 		NPCX_PDIR(port) |= mask;
 
 	/* Lock GPIO output and configuration if need */
-#if defined(CHIP_FAMILY_NPCX7)
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	if (flags & GPIO_LOCKED)
 		NPCX_PLOCK_CTL(port) |= mask;
 #endif
@@ -529,6 +538,8 @@ void gpio_pre_init(void)
 	 * for more information. It will be fixed in next chip.
 	 */
 	SET_BIT(NPCX_DEVCNT, 7);
+#endif
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	/* Lock VCC_RST# alternative bit in case switch to GPO77 unexpectedly */
 	SET_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_VCC1_RST_LK);
 #endif
@@ -605,32 +616,6 @@ void gpio_pre_init(void)
 #endif
 }
 
-/* List of GPIO IRQs to enable. Don't automatically enable interrupts for
- * the keyboard input GPIO bank - that's handled separately. Of course the
- * bank is different for different systems. */
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(NPCX_IRQ_MTC_WKINTAD_0);
-	task_enable_irq(NPCX_IRQ_WKINTEFGH_0);
-	task_enable_irq(NPCX_IRQ_WKINTC_0);
-	task_enable_irq(NPCX_IRQ_TWD_WKINTB_0);
-	task_enable_irq(NPCX_IRQ_WKINTA_1);
-	task_enable_irq(NPCX_IRQ_WKINTB_1);
-#ifndef HAS_TASK_KEYSCAN
-	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
-#endif
-	task_enable_irq(NPCX_IRQ_WKINTD_1);
-	task_enable_irq(NPCX_IRQ_WKINTE_1);
-	task_enable_irq(NPCX_IRQ_WKINTF_1);
-	task_enable_irq(NPCX_IRQ_WKINTG_1);
-	task_enable_irq(NPCX_IRQ_WKINTH_1);
-#if defined(CHIP_FAMILY_NPCX7)
-	task_enable_irq(NPCX_IRQ_WKINTFG_2);
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
 /*****************************************************************************/
 /* Interrupt handlers */
 
@@ -640,7 +625,7 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
  * @param wui_int wui table & group for GPIO interrupt no.
  */
 
-static void gpio_interrupt(struct npcx_wui wui_int)
+void gpio_interrupt(struct npcx_wui wui_int)
 {
 	int i;
 	uint8_t wui_mask;
@@ -671,154 +656,6 @@ static void gpio_interrupt(struct npcx_wui wui_int)
 		NPCX_WKPCL(table, group) = wui_mask;
 }
 
-/**
- * Handlers for each GPIO port.  These read and clear the interrupt bits for
- * the port, then call the master handler above.
- */
-
-#define GPIO_IRQ_FUNC(_irq_func, wui_int)		\
-void _irq_func(void)					\
-{							\
-	gpio_interrupt(wui_int);			\
-}
-
-/* If we need to handle the other type interrupts except GPIO, add code here */
-void __gpio_wk0efgh_interrupt(void)
-{
-#ifdef CONFIG_HOSTCMD_X86
-	/* Pending bit 7 or 6 or 5? */
-	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0 , MIWU_GROUP_5), 6) &&
-	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5), 6)) {
-		/* Disable host wake-up */
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-		/* Clear pending bit of WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-	}
-#ifdef CONFIG_HOSTCMD_ESPI
-	else if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5) &&
-		 IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5))
-		espi_espirst_handler();
-#else
-	else if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7) &&
-		 IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7))
-		lpc_lreset_pltrst_handler();
-#endif
-	else
-#endif
-	{
-		gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_5));
-		gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_6));
-		gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_7));
-		gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_8));
-	}
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static void set_rtc_host_event(void)
-{
-	host_set_single_event(EC_HOST_EVENT_RTC);
-}
-DECLARE_DEFERRED(set_rtc_host_event);
-#endif
-
-void __gpio_rtc_interrupt(void)
-{
-	/* Check pending bit 7 */
-#ifdef CONFIG_HOSTCMD_RTC
-	if (NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_4) & 0x80) {
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_4), 7);
-		hook_call_deferred(&set_rtc_host_event_data, 0);
-		return;
-	}
-#endif
-#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
-	(CONFIG_CONSOLE_UART == 1)
-	/* Handle the interrupt from UART wakeup event */
-	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6) &&
-	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_1), 6)) {
-		/*
-		 * Disable WKEN bit to avoid the other unnecessary interrupts
-		 * from the coming data bits after the start bit. (Pending bit
-		 * of CR_SIN is set when a high-to-low transaction occurs.)
-		 */
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6);
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_1), 6);
-		/* Notify the clock module that the console is in use. */
-		clock_refresh_console_in_use();
-		return;
-	}
-#endif
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1));
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4));
-}
-
-void __gpio_wk1h_interrupt(void)
-{
-#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
-	(CONFIG_CONSOLE_UART == 0)
-	/* Handle the interrupt from UART wakeup event */
-	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7) &&
-	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_1, MIWU_GROUP_8), 7)) {
-		/*
-		 * Disable WKEN bit to avoid the other unnecessary interrupts
-		 * from the coming data bits after the start bit. (Pending bit
-		 * of CR_SIN is set when a high-to-low transaction occurs.)
-		 */
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7);
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_1, MIWU_GROUP_8), 7);
-		/* Notify the clock module that the console is in use. */
-		clock_refresh_console_in_use();
-	} else
-#endif
-		gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8));
-}
-
-GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2));
-GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3));
-GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1));
-GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2));
-#ifndef HAS_TASK_KEYSCAN
-/* Delcare GPIO irq functions for KSI pins if there's no keyboard scan task, */
-GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3));
-#endif
-GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4));
-GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5));
-GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6));
-GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7));
-#if defined(CHIP_FAMILY_NPCX7)
-GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
-#endif
-
-DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,  __gpio_wk0b_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTC_0,      __gpio_wk0c_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0,   __gpio_wk0efgh_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTA_1,      __gpio_wk1a_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTB_1,      __gpio_wk1b_interrupt, 3);
-#ifndef HAS_TASK_KEYSCAN
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,  __gpio_wk1c_interrupt, 3);
-#endif
-DECLARE_IRQ(NPCX_IRQ_WKINTD_1,      __gpio_wk1d_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_1,      __gpio_wk1e_interrupt, 3);
-#ifdef CONFIG_HOSTCMD_SPS
-/*
- * HACK: Make CS GPIO P2 to improve SHI reliability.
- * TODO: Increase CS-assertion-to-transaction-start delay on host to
- * accommodate P3 CS interrupt.
- */
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 2);
-#else
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 3);
-#endif
-DECLARE_IRQ(NPCX_IRQ_WKINTG_1,      __gpio_wk1g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_1,      __gpio_wk1h_interrupt, 3);
-#if defined(CHIP_FAMILY_NPCX7)
-DECLARE_IRQ(NPCX_IRQ_WKINTFG_2,     __gpio_wk2fg_interrupt, 3);
-#endif
-
 #undef GPIO_IRQ_FUNC
 #if DEBUG_GPIO && defined(CONFIG_LOW_POWER_IDLE)
 /*
diff --git a/chip/npcx/gpio_chip-npcx9.h b/chip/npcx/gpio_chip-npcx9.h
new file mode 100644
index 0000000000..a80a1b899a
--- /dev/null
+++ b/chip/npcx/gpio_chip-npcx9.h
@@ -0,0 +1,462 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_GPIO_CHIP_NPCX9_H
+#define __CROS_EC_GPIO_CHIP_NPCX9_H
+
+/*****************************************************************************/
+/* Macro functions for MIWU mapping table */
+
+/* MIWU0 */
+/* Group A: NPCX_IRQ_MTC_WKINTAD_0 */
+#define NPCX_WUI_GPIO_8_0 WUI(0, MIWU_GROUP_1, 0)
+#define NPCX_WUI_GPIO_8_1 WUI(0, MIWU_GROUP_1, 1)
+#define NPCX_WUI_GPIO_8_2 WUI(0, MIWU_GROUP_1, 2)
+#define NPCX_WUI_GPIO_8_3 WUI(0, MIWU_GROUP_1, 3)
+#define NPCX_WUI_GPIO_8_6 WUI(0, MIWU_GROUP_1, 6)
+#define NPCX_WUI_GPIO_8_7 WUI(0, MIWU_GROUP_1, 7)
+
+/* Group B: NPCX_IRQ_TWD_WKINTB_0 */
+#define NPCX_WUI_GPIO_9_0 WUI(0, MIWU_GROUP_2, 0)
+#define NPCX_WUI_GPIO_9_1 WUI(0, MIWU_GROUP_2, 1)
+#define NPCX_WUI_GPIO_9_2 WUI(0, MIWU_GROUP_2, 2)
+#define NPCX_WUI_GPIO_9_3 WUI(0, MIWU_GROUP_2, 3)
+#define NPCX_WUI_GPIO_9_4 WUI(0, MIWU_GROUP_2, 4)
+#define NPCX_WUI_GPIO_9_5 WUI(0, MIWU_GROUP_2, 5)
+
+/* Group C: NPCX_IRQ_WKINTC_0 */
+#define NPCX_WUI_GPIO_9_6 WUI(0, MIWU_GROUP_3, 0)
+#define NPCX_WUI_GPIO_9_7 WUI(0, MIWU_GROUP_3, 1)
+#define NPCX_WUI_GPIO_A_0 WUI(0, MIWU_GROUP_3, 2)
+#define NPCX_WUI_GPIO_A_1 WUI(0, MIWU_GROUP_3, 3)
+#define NPCX_WUI_GPIO_A_2 WUI(0, MIWU_GROUP_3, 4)
+#define NPCX_WUI_GPIO_A_3 WUI(0, MIWU_GROUP_3, 5)
+#define NPCX_WUI_GPIO_A_4 WUI(0, MIWU_GROUP_3, 6)
+#define NPCX_WUI_GPIO_A_5 WUI(0, MIWU_GROUP_3, 7)
+
+/* Group D: NPCX_IRQ_MTC_WKINTAD_0 */
+#define NPCX_WUI_GPIO_A_6 WUI(0, MIWU_GROUP_4, 0)
+#define NPCX_WUI_GPIO_A_7 WUI(0, MIWU_GROUP_4, 1)
+#define NPCX_WUI_GPIO_B_0 WUI(0, MIWU_GROUP_4, 2)
+#define NPCX_WUI_GPIO_B_1 WUI(0, MIWU_GROUP_4, 5)
+#define NPCX_WUI_GPIO_B_2 WUI(0, MIWU_GROUP_4, 6)
+
+/* Group E: NPCX_IRQ_WKINTEFGH_0 */
+#define NPCX_WUI_GPIO_B_3 WUI(0, MIWU_GROUP_5, 0)
+#define NPCX_WUI_GPIO_B_4 WUI(0, MIWU_GROUP_5, 1)
+#define NPCX_WUI_GPIO_B_5 WUI(0, MIWU_GROUP_5, 2)
+#define NPCX_WUI_GPIO_B_7 WUI(0, MIWU_GROUP_5, 4)
+
+/* Group F: NPCX_IRQ_WKINTEFGH_0 */
+#define NPCX_WUI_GPIO_C_0 WUI(0, MIWU_GROUP_6, 0)
+#define NPCX_WUI_GPIO_C_1 WUI(0, MIWU_GROUP_6, 1)
+#define NPCX_WUI_GPIO_C_2 WUI(0, MIWU_GROUP_6, 2)
+#define NPCX_WUI_GPIO_C_3 WUI(0, MIWU_GROUP_6, 3)
+#define NPCX_WUI_GPIO_C_4 WUI(0, MIWU_GROUP_6, 4)
+#define NPCX_WUI_GPIO_C_5 WUI(0, MIWU_GROUP_6, 5)
+#define NPCX_WUI_GPIO_C_6 WUI(0, MIWU_GROUP_6, 6)
+#define NPCX_WUI_GPIO_C_7 WUI(0, MIWU_GROUP_6, 7)
+
+/* Group G: NPCX_IRQ_WKINTEFGH_0 */
+#define NPCX_WUI_GPIO_D_0 WUI(0, MIWU_GROUP_7, 0)
+#define NPCX_WUI_GPIO_D_1 WUI(0, MIWU_GROUP_7, 1)
+#define NPCX_WUI_GPIO_D_2 WUI(0, MIWU_GROUP_7, 2)
+#define NPCX_WUI_GPIO_D_3 WUI(0, MIWU_GROUP_7, 3)
+#define NPCX_WUI_GPIO_D_4 WUI(0, MIWU_GROUP_7, 4)
+#define NPCX_WUI_GPIO_D_5 WUI(0, MIWU_GROUP_7, 5)
+#define NPCX_WUI_GPIO_E_0 WUI(0, MIWU_GROUP_7, 7)
+
+/* Group H: NPCX_IRQ_WKINTEFGH_0 */
+#define NPCX_WUI_GPIO_E_1 WUI(0, MIWU_GROUP_8, 0)
+#define NPCX_WUI_GPIO_E_2 WUI(0, MIWU_GROUP_8, 1)
+#define NPCX_WUI_GPIO_E_3 WUI(0, MIWU_GROUP_8, 2)
+#define NPCX_WUI_GPIO_E_4 WUI(0, MIWU_GROUP_8, 3)
+#define NPCX_WUI_GPIO_E_5 WUI(0, MIWU_GROUP_8, 4)
+#define NPCX_WUI_GPIO_F_0 WUI(0, MIWU_GROUP_8, 5)
+#define NPCX_WUI_GPIO_F_3 WUI(0, MIWU_GROUP_8, 6)
+
+/* MIWU1 */
+/* Group A: NPCX_IRQ_WKINTA_1 */
+#define NPCX_WUI_GPIO_0_0 WUI(1, MIWU_GROUP_1, 0)
+#define NPCX_WUI_GPIO_0_1 WUI(1, MIWU_GROUP_1, 1)
+#define NPCX_WUI_GPIO_0_2 WUI(1, MIWU_GROUP_1, 2)
+#define NPCX_WUI_GPIO_0_3 WUI(1, MIWU_GROUP_1, 3)
+#define NPCX_WUI_GPIO_0_4 WUI(1, MIWU_GROUP_1, 4)
+#define NPCX_WUI_GPIO_0_5 WUI(1, MIWU_GROUP_1, 5)
+#define NPCX_WUI_GPIO_0_6 WUI(1, MIWU_GROUP_1, 6)
+#define NPCX_WUI_GPIO_0_7 WUI(1, MIWU_GROUP_1, 7)
+
+/* Group B: NPCX_IRQ_WKINTB_1 */
+#define NPCX_WUI_GPIO_1_0 WUI(1, MIWU_GROUP_2, 0)
+#define NPCX_WUI_GPIO_1_1 WUI(1, MIWU_GROUP_2, 1)
+#define NPCX_WUI_GPIO_F_4 WUI(1, MIWU_GROUP_2, 2)
+#define NPCX_WUI_GPIO_1_4 WUI(1, MIWU_GROUP_2, 4)
+#define NPCX_WUI_GPIO_1_5 WUI(1, MIWU_GROUP_2, 5)
+#define NPCX_WUI_GPIO_1_6 WUI(1, MIWU_GROUP_2, 6)
+#define NPCX_WUI_GPIO_1_7 WUI(1, MIWU_GROUP_2, 7)
+
+/* Group C: NPCX_IRQ_KSI_WKINTC_1 */
+#define NPCX_WUI_GPIO_3_1 WUI(1, MIWU_GROUP_3, 0)
+#define NPCX_WUI_GPIO_3_0 WUI(1, MIWU_GROUP_3, 1)
+#define NPCX_WUI_GPIO_2_7 WUI(1, MIWU_GROUP_3, 2)
+#define NPCX_WUI_GPIO_2_6 WUI(1, MIWU_GROUP_3, 3)
+#define NPCX_WUI_GPIO_2_5 WUI(1, MIWU_GROUP_3, 4)
+#define NPCX_WUI_GPIO_2_4 WUI(1, MIWU_GROUP_3, 5)
+#define NPCX_WUI_GPIO_2_3 WUI(1, MIWU_GROUP_3, 6)
+#define NPCX_WUI_GPIO_2_2 WUI(1, MIWU_GROUP_3, 7)
+
+/* Group D: NPCX_IRQ_WKINTD_1 */
+#define NPCX_WUI_GPIO_2_0 WUI(1, MIWU_GROUP_4, 0)
+#define NPCX_WUI_GPIO_2_1 WUI(1, MIWU_GROUP_4, 1)
+#define NPCX_WUI_GPIO_F_5 WUI(1, MIWU_GROUP_4, 2)
+#define NPCX_WUI_GPIO_3_3 WUI(1, MIWU_GROUP_4, 3)
+#define NPCX_WUI_GPIO_3_4 WUI(1, MIWU_GROUP_4, 4)
+#define NPCX_WUI_GPIO_3_6 WUI(1, MIWU_GROUP_4, 6)
+#define NPCX_WUI_GPIO_3_7 WUI(1, MIWU_GROUP_4, 7)
+
+/* Group E: NPCX_IRQ_WKINTE_1 */
+#define NPCX_WUI_GPIO_4_0 WUI(1, MIWU_GROUP_5, 0)
+#define NPCX_WUI_GPIO_4_1 WUI(1, MIWU_GROUP_5, 1)
+#define NPCX_WUI_GPIO_4_2 WUI(1, MIWU_GROUP_5, 2)
+#define NPCX_WUI_GPIO_4_3 WUI(1, MIWU_GROUP_5, 3)
+#define NPCX_WUI_GPIO_4_4 WUI(1, MIWU_GROUP_5, 4)
+#define NPCX_WUI_GPIO_4_5 WUI(1, MIWU_GROUP_5, 5)
+#define NPCX_WUI_GPIO_4_6 WUI(1, MIWU_GROUP_5, 6)
+#define NPCX_WUI_GPIO_4_7 WUI(1, MIWU_GROUP_5, 7)
+
+/* Group F: NPCX_IRQ_WKINTF_1 */
+#define NPCX_WUI_GPIO_5_0 WUI(1, MIWU_GROUP_6, 0)
+#define NPCX_WUI_GPIO_5_1 WUI(1, MIWU_GROUP_6, 1)
+#define NPCX_WUI_GPIO_5_2 WUI(1, MIWU_GROUP_6, 2)
+#define NPCX_WUI_GPIO_5_3 WUI(1, MIWU_GROUP_6, 3)
+#define NPCX_WUI_GPIO_5_4 WUI(1, MIWU_GROUP_6, 4)
+#define NPCX_WUI_GPIO_5_5 WUI(1, MIWU_GROUP_6, 5)
+#define NPCX_WUI_GPIO_5_6 WUI(1, MIWU_GROUP_6, 6)
+#define NPCX_WUI_GPIO_5_7 WUI(1, MIWU_GROUP_6, 7)
+
+/* Group G: NPCX_IRQ_WKINTG_1 */
+#define NPCX_WUI_GPIO_6_0 WUI(1, MIWU_GROUP_7, 0)
+#define NPCX_WUI_GPIO_6_1 WUI(1, MIWU_GROUP_7, 1)
+#define NPCX_WUI_GPIO_6_2 WUI(1, MIWU_GROUP_7, 2)
+#define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3)
+#define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4)
+
+/* Group H: NPCX_IRQ_WKINTH_1 */
+#define NPCX_WUI_GPIO_7_0 WUI(1, MIWU_GROUP_8, 0)
+#define NPCX_WUI_GPIO_6_7 WUI(1, MIWU_GROUP_8, 1)
+#define NPCX_WUI_GPIO_7_2 WUI(1, MIWU_GROUP_8, 2)
+#define NPCX_WUI_GPIO_7_3 WUI(1, MIWU_GROUP_8, 3)
+#define NPCX_WUI_GPIO_7_4 WUI(1, MIWU_GROUP_8, 4)
+#define NPCX_WUI_GPIO_7_5 WUI(1, MIWU_GROUP_8, 5)
+#define NPCX_WUI_GPIO_7_6 WUI(1, MIWU_GROUP_8, 6)
+
+/* MIWU2 */
+/* Group F: NPCX_IRQ_WKINTFG_2 */
+#define NPCX_WUI_GPIO_F_1 WUI(2, MIWU_GROUP_6, 1)
+#define NPCX_WUI_GPIO_F_2 WUI(2, MIWU_GROUP_6, 2)
+#define NPCX_WUI_GPIO_B_6 WUI(2, MIWU_GROUP_6, 6)
+
+/* Others GPO without MIWU functionality */
+#define NPCX_WUI_GPIO_1_2 WUI_NONE
+#define NPCX_WUI_GPIO_1_3 WUI_NONE /* Software strap pin GP_SEL1_L */
+#define NPCX_WUI_GPIO_3_2 WUI_NONE
+#define NPCX_WUI_GPIO_3_5 WUI_NONE
+#define NPCX_WUI_GPIO_6_5 WUI_NONE /* Software strap pin FLPRG_L */
+#define NPCX_WUI_GPIO_6_6 WUI_NONE
+#define NPCX_WUI_GPIO_7_7 WUI_NONE
+#define NPCX_WUI_GPIO_8_5 WUI_NONE /* PSL_OUT/GPO85 */
+#define NPCX_WUI_GPIO_D_6 WUI_NONE /* strap pin SHDF_ESPI */
+#define NPCX_WUI_GPIO_D_7 WUI_NONE /* PSL_GPO/GPOD7 */
+
+/*****************************************************************************/
+/* Macro functions for Alternative mapping table */
+
+/* I2C Module */
+#define NPCX_ALT_GPIO_B_4 ALT(B, 4, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SDA0 */
+#define NPCX_ALT_GPIO_B_5 ALT(B, 5, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SCL0 */
+#define NPCX_ALT_GPIO_B_2 ALT(B, 2, NPCX_ALT(2, I2C7_0_SL)) /* SMB7SDA0 */
+#define NPCX_ALT_GPIO_B_3 ALT(B, 3, NPCX_ALT(2, I2C7_0_SL)) /* SMB7SCL0 */
+#define NPCX_ALT_GPIO_8_7 ALT(8, 7, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SDA0 */
+#define NPCX_ALT_GPIO_9_0 ALT(9, 0, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SCL0 */
+#define NPCX_ALT_GPIO_9_1 ALT(9, 1, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SDA0 */
+#define NPCX_ALT_GPIO_9_2 ALT(9, 2, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SCL0 */
+#define NPCX_ALT_GPIO_3_6 ALT(3, 6, NPCX_ALT(2, I2C5_0_SL)) /* SMB5SDA0 */
+#define NPCX_ALT_GPIO_3_3 ALT(3, 3, NPCX_ALT(2, I2C5_0_SL)) /* SMB5SCL0 */
+#define NPCX_ALT_GPIO_D_0 ALT(D, 0, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SDA0 */
+#define NPCX_ALT_GPIO_D_1 ALT(D, 1, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SCL0 */
+
+#define NPCX_ALT_GPIO_F_2 ALT(F, 2, NPCX_ALT(6, I2C4_1_SL)) /* SMB4SDA1 */
+#define NPCX_ALT_GPIO_F_3 ALT(F, 3, NPCX_ALT(6, I2C4_1_SL)) /* SMB4SCL1 */
+#define NPCX_ALT_GPIO_F_4 ALT(F, 4, NPCX_ALT(6, I2C5_1_SL)) /* SMB5SDA1 */
+#define NPCX_ALT_GPIO_F_5 ALT(F, 5, NPCX_ALT(6, I2C5_1_SL)) /* SMB5SCL1 */
+#define NPCX_ALT_GPIO_E_3 ALT(E, 3, NPCX_ALT(6, I2C6_1_SL)) /* SMB6SDA1 */
+#define NPCX_ALT_GPIO_E_4 ALT(E, 4, NPCX_ALT(6, I2C6_1_SL)) /* SMB6SCL1 */
+/* Pin-Mux for PWM1/SMB6_0 */
+#if NPCX9_PWM1_SEL
+#define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */
+#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL))   /* PWM1 */
+#else
+#define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */
+#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */
+#endif
+
+/* ADC Module */
+#define NPCX_ALT_GPIO_4_5 ALT(4, 5, NPCX_ALT(6, ADC0_SL)) /* ADC0  */
+#define NPCX_ALT_GPIO_4_4 ALT(4, 4, NPCX_ALT(6, ADC1_SL)) /* ADC1  */
+#define NPCX_ALT_GPIO_4_3 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2  */
+#define NPCX_ALT_GPIO_4_2 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3  */
+#define NPCX_ALT_GPIO_4_1 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4  */
+#ifdef CONFIG_PS2
+#define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */
+#define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */
+#else
+#define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(F, ADC5_SL)) /* ADC5  */
+#define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(F, ADC6_SL)) /* ADC6  */
+#endif
+#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL))  /* ADC8  */
+#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL))  /* ADC7  */
+#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL))  /* ADC9  */
+#define NPCX_ALT_GPIO_E_0 ALT(E, 0, NPCX_ALT(F, ADC10_SL)) /* AD10  */
+#define NPCX_ALT_GPIO_C_7 ALT(C, 7, NPCX_ALT(F, ADC11_SL)) /* AD11  */
+
+/* PS/2 Module */
+#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL))  /* PS2_CLK0 */
+#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL))  /* PS2_DATA0 */
+#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL))  /* PS2_CLK1 */
+#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL))  /* PS2_DATA1 */
+#define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */
+
+/* UART Module */
+#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 */
+#define NPCX_ALT_GPIO_6_5 ALT(6, 5, NPCX_ALT(J, CR_SOUT1_SL2))/* CR_SOUT1_SL2 */
+#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(J, CR_SIN2_SL))  /* CR_SIN2_SL */
+#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL */
+#define NPCX_ALT_GPIO_D_4 ALT(D, 4, NPCX_ALT(J, CR_SIN3_SL))  /* CR_SIN3_SL */
+#define NPCX_ALT_GPIO_D_6 ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL */
+
+/* PWM Module */
+#define NPCX_ALT_GPIO_C_3 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */
+#define NPCX_ALT_GPIO_C_4 ALT(C, 4, NPCX_ALT(4, PWM2_SL)) /* PWM2 */
+#define NPCX_ALT_GPIO_8_0 ALT(8, 0, NPCX_ALT(4, PWM3_SL)) /* PWM3 */
+#define NPCX_ALT_GPIO_B_6 ALT(B, 6, NPCX_ALT(4, PWM4_SL)) /* PWM4 */
+#define NPCX_ALT_GPIO_B_7 ALT(B, 7, NPCX_ALT(4, PWM5_SL)) /* PWM5 */
+#define NPCX_ALT_GPIO_C_0 ALT(C, 0, NPCX_ALT(4, PWM6_SL)) /* PWM6 */
+#define NPCX_ALT_GPIO_6_0 ALT(6, 0, NPCX_ALT(4, PWM7_SL)) /* PWM7 */
+
+/* MFT Module */
+#define NPCX_ALT_GPIO_4_0 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */
+#define NPCX_ALT_GPIO_7_3 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */
+#define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */
+#ifdef CONFIG_PS2
+#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */
+#else
+#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */
+#endif
+
+/* Keyboard Scan Module */
+#define NPCX_ALT_GPIO_3_1 ALT(3, 1, NPCX_ALT_INV(7, NO_KSI0_SL)) /* KSI0 */
+#define NPCX_ALT_GPIO_3_0 ALT(3, 0, NPCX_ALT_INV(7, NO_KSI1_SL)) /* KSI1 */
+#define NPCX_ALT_GPIO_2_7 ALT(2, 7, NPCX_ALT_INV(7, NO_KSI2_SL)) /* KSI2 */
+#define NPCX_ALT_GPIO_2_6 ALT(2, 6, NPCX_ALT_INV(7, NO_KSI3_SL)) /* KSI3 */
+#define NPCX_ALT_GPIO_2_5 ALT(2, 5, NPCX_ALT_INV(7, NO_KSI4_SL)) /* KSI4 */
+#define NPCX_ALT_GPIO_2_4 ALT(2, 4, NPCX_ALT_INV(7, NO_KSI5_SL)) /* KSI5 */
+#define NPCX_ALT_GPIO_2_3 ALT(2, 3, NPCX_ALT_INV(7, NO_KSI6_SL)) /* KSI6 */
+#define NPCX_ALT_GPIO_2_2 ALT(2, 2, NPCX_ALT_INV(7, NO_KSI7_SL)) /* KSI7 */
+#define NPCX_ALT_GPIO_2_1 ALT(2, 1, NPCX_ALT_INV(8, NO_KSO00_SL)) /* KSO00 */
+#define NPCX_ALT_GPIO_2_0 ALT(2, 0, NPCX_ALT_INV(8, NO_KSO01_SL)) /* KSO01 */
+#define NPCX_ALT_GPIO_1_7 ALT(1, 7, NPCX_ALT_INV(8, NO_KSO02_SL)) /* KSO02 */
+#define NPCX_ALT_GPIO_1_6 ALT(1, 6, NPCX_ALT_INV(8, NO_KSO03_SL)) /* KSO03 */
+#define NPCX_ALT_GPIO_1_5 ALT(1, 5, NPCX_ALT_INV(8, NO_KSO04_SL)) /* KSO04 */
+#define NPCX_ALT_GPIO_1_4 ALT(1, 4, NPCX_ALT_INV(8, NO_KSO05_SL)) /* KSO05 */
+#define NPCX_ALT_GPIO_1_3 ALT(1, 3, NPCX_ALT_INV(8, NO_KSO06_SL)) /* KSO06 */
+#define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */
+/* KSO08 & CR_SOUT */
+#define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL))
+ /* KSO09 & CR_SIN */
+#define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL))
+#define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */
+#define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */
+#define NPCX_ALT_GPIO_0_5 ALT(0, 5, NPCX_ALT_INV(9, NO_KSO12_SL)) /* KSO12 */
+#define NPCX_ALT_GPIO_0_4 ALT(0, 4, NPCX_ALT_INV(9, NO_KSO13_SL)) /* KSO13 */
+#define NPCX_ALT_GPIO_8_2 ALT(8, 2, NPCX_ALT_INV(9, NO_KSO14_SL)) /* KSO14 */
+#define NPCX_ALT_GPIO_8_3 ALT(8, 3, NPCX_ALT_INV(9, NO_KSO15_SL)) /* KSO15 */
+#define NPCX_ALT_GPIO_0_3 ALT(0, 3, NPCX_ALT_INV(A, NO_KSO16_SL)) /* KSO16 */
+#define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */
+
+/* PSL module */
+#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */
+#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */
+#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL))      /* PSL_IN3 */
+#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL))      /* PSL_IN4 */
+#define NPCX_ALT_GPIO_D_7 ALT(D, 7, NPCX_ALT(G, PSL_GPO_SL))      /* PSL_GPO */
+
+/* SPI Module */
+#define NPCX_ALT_GPIO_9_5 ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */
+#define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */
+#define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */
+
+#define NPCX_ALT_TABLE { \
+	NPCX_ALT_GPIO_0_0 /* PSL_IN2 */               \
+	NPCX_ALT_GPIO_0_1 /* PSL_IN3 */               \
+	NPCX_ALT_GPIO_0_2 /* PSL_IN4 */               \
+	NPCX_ALT_GPIO_0_3 /* KSO16 */                 \
+	NPCX_ALT_GPIO_0_4 /* KSO13 */                 \
+	NPCX_ALT_GPIO_0_5 /* KSO12 */                 \
+	NPCX_ALT_GPIO_0_6 /* KSO11 */                 \
+	NPCX_ALT_GPIO_0_7 /* KSO10 */                 \
+	NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */        \
+	NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */       \
+	NPCX_ALT_GPIO_1_2 /* KSO07 */                 \
+	NPCX_ALT_GPIO_1_3 /* KSO06 */                 \
+	NPCX_ALT_GPIO_1_4 /* KSO05 */                 \
+	NPCX_ALT_GPIO_1_5 /* KSO04 */                 \
+	NPCX_ALT_GPIO_1_6 /* KSO03 */                 \
+	NPCX_ALT_GPIO_1_7 /* KSO02 */                 \
+	NPCX_ALT_GPIO_2_0 /* KSO01 */                 \
+	NPCX_ALT_GPIO_2_1 /* KSO00 */                 \
+	NPCX_ALT_GPIO_2_2 /* KSI7 */                  \
+	NPCX_ALT_GPIO_2_3 /* KSI6 */                  \
+	NPCX_ALT_GPIO_2_4 /* KSI5 */                  \
+	NPCX_ALT_GPIO_2_5 /* KSI4 */                  \
+	NPCX_ALT_GPIO_2_6 /* KSI3 */                  \
+	NPCX_ALT_GPIO_2_7 /* KSI2 */                  \
+	NPCX_ALT_GPIO_3_0 /* KSI1 */                  \
+	NPCX_ALT_GPIO_3_1 /* KSI0 */                  \
+	NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */              \
+	NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */         \
+	NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */              \
+	NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */         \
+	NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */              \
+	NPCX_ALT_GPIO_4_1 /* ADC4  */                 \
+	NPCX_ALT_GPIO_4_2 /* ADC3  */                 \
+	NPCX_ALT_GPIO_4_3 /* ADC2  */                 \
+	NPCX_ALT_GPIO_4_4 /* ADC1  */                 \
+	NPCX_ALT_GPIO_4_5 /* ADC0  */                 \
+	NPCX_ALT_GPIO_6_0 /* PWM7 */                  \
+	NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */              \
+	NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */              \
+	NPCX_ALT_GPIO_6_4 /* CR_SIN1_SL2 */           \
+	NPCX_ALT_GPIO_6_5 /* CR_SOUT1_SL2 */          \
+	NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */              \
+	NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */              \
+	NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */              \
+	NPCX_ALT_GPIO_7_5 /* CR_SIN2_SL */            \
+	NPCX_ALT_GPIO_8_0 /* PWM3 */                  \
+	NPCX_ALT_GPIO_8_2 /* KSO14 */                 \
+	NPCX_ALT_GPIO_8_3 /* KSO15 */                 \
+	NPCX_ALT_GPIO_8_6 /* CR_SOUT2_SL */           \
+	NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */              \
+	NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */              \
+	NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */              \
+	NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */              \
+	NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */              \
+	NPCX_ALT_GPIO_9_5 /* SPIP_MISO */             \
+	NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */             \
+	NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */             \
+	NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */     \
+	NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */     \
+	NPCX_ALT_GPIO_B_1 /* KSO17 */                 \
+	NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */              \
+	NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */              \
+	NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */              \
+	NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */              \
+	NPCX_ALT_GPIO_B_6 /* PWM4 */                  \
+	NPCX_ALT_GPIO_B_7 /* PWM5 */                  \
+	NPCX_ALT_GPIO_C_0 /* PWM6 */                  \
+	NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */              \
+	NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */       \
+	NPCX_ALT_GPIO_C_3 /* PWM0 */                  \
+	NPCX_ALT_GPIO_C_4 /* PWM2 */                  \
+	NPCX_ALT_GPIO_C_7 /* ADC11 */                 \
+	NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */              \
+	NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */              \
+	NPCX_ALT_GPIO_D_2 /* PSL_IN1 */               \
+	NPCX_ALT_GPIO_D_4 /* CR_SIN3_SL */            \
+	NPCX_ALT_GPIO_D_6 /* CR_SOUT3_SL */           \
+	NPCX_ALT_GPIO_D_7 /* PSL_GPO */               \
+	NPCX_ALT_GPIO_E_0 /* ADC10 */                 \
+	NPCX_ALT_GPIO_E_1 /* ADC7  */                 \
+	NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */              \
+	NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */              \
+	NPCX_ALT_GPIO_F_0 /* ADC9  */                 \
+	NPCX_ALT_GPIO_F_1 /* ADC8  */                 \
+	NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */              \
+	NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */              \
+	NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */              \
+	NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */              \
+}
+
+/*****************************************************************************/
+/* Macro functions for Low-Voltage mapping table */
+
+/* Low-Voltage GPIO Control 0 */
+#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
+#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
+#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
+#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
+#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
+#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
+#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
+#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
+
+/* Low-Voltage GPIO Control 1 */
+#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
+#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
+#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
+#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
+#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
+#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
+#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
+
+/* Low-Voltage GPIO Control 2 */
+#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
+#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
+#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
+#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
+#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
+
+/* Low-Voltage GPIO Control 3 */
+#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
+#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
+#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
+#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
+#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
+#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
+#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
+
+/* Low-Voltage GPIO Control 4 */
+#define NPCX_LVOL_CTRL_4_0  NPCX_GPIO(8, 6)
+#define NPCX_LVOL_CTRL_4_1  NPCX_GPIO(C, 2)
+#define NPCX_LVOL_CTRL_4_2  NPCX_GPIO(F, 3)
+#define NPCX_LVOL_CTRL_4_3  NPCX_GPIO(F, 2)
+#define NPCX_LVOL_CTRL_4_4  NPCX_GPIO(F, 5)
+#define NPCX_LVOL_CTRL_4_5  NPCX_GPIO(F, 4)
+#define NPCX_LVOL_CTRL_4_6  NPCX_GPIO(E, 4)
+#define NPCX_LVOL_CTRL_4_7  NPCX_GPIO(E, 3)
+
+/* Low-Voltage GPIO Control 5 */
+#define NPCX_LVOL_CTRL_5_0  NPCX_GPIO(7, 2)
+#define NPCX_LVOL_CTRL_5_1  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_2  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_3  NPCX_GPIO(5, 0)
+#define NPCX_LVOL_CTRL_5_4  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_5  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_6  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_7  NPCX_GPIO_NONE
+
+/* 6 Low-Voltage Control Groups on npcx7 */
+#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
+			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
+			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
+			  { NPCX_LVOL_CTRL_ITEMS(3), }, \
+			  { NPCX_LVOL_CTRL_ITEMS(4), }, \
+			  { NPCX_LVOL_CTRL_ITEMS(5), }, }
+
+#endif /* __CROS_EC_GPIO_CHIP_NPCX9_H */
diff --git a/chip/npcx/gpio_chip.h b/chip/npcx/gpio_chip.h
index 6282794e44..2d0b2b4e9b 100644
--- a/chip/npcx/gpio_chip.h
+++ b/chip/npcx/gpio_chip.h
@@ -29,7 +29,8 @@ struct npcx_wui {
 			.bit = NPCX_DEVALT##grp##_##pin, .inverted = 0 })
 #define NPCX_ALT_INV(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \
 			.bit = NPCX_DEVALT##grp##_##pin, .inverted = 1 })
-#define ALT(port, index, alt) { NPCX_GPIO(port, index), alt },
+#define ALT(port, index, _alt) { .gpio = NPCX_GPIO(port, index), \
+			.alt = (_alt) },
 
 #define NPCX_LVOL_CTRL_ITEMS(ctrl) { NPCX_LVOL_CTRL_##ctrl##_0, \
 				     NPCX_LVOL_CTRL_##ctrl##_1, \
@@ -54,6 +55,8 @@ void npcx_gpio2uart(void);
 /* Set input buffer of all 1.8v i2c ports. */
 void gpio_enable_1p8v_i2c_wake_up_input(int enable);
 
+void gpio_interrupt(struct npcx_wui wui_int);
+
 /*
  * Include the MIWU, alternative and low-Voltage macro functions for GPIOs
  * depends on Nuvoton chip series.
@@ -62,6 +65,8 @@ void gpio_enable_1p8v_i2c_wake_up_input(int enable);
 #include "gpio_chip-npcx5.h"
 #elif defined(CHIP_FAMILY_NPCX7)
 #include "gpio_chip-npcx7.h"
+#elif defined(CHIP_FAMILY_NPCX9)
+#include "gpio_chip-npcx9.h"
 #else
 #error "Unsupported chip family"
 #endif
diff --git a/chip/npcx/lpc_chip.h b/chip/npcx/lpc_chip.h
index c2f80158af..607fdde5fa 100644
--- a/chip/npcx/lpc_chip.h
+++ b/chip/npcx/lpc_chip.h
@@ -11,13 +11,10 @@
 /* For host registers initialization via SIB module */
 void host_register_init(void);
 
-#ifdef CONFIG_HOSTCMD_ESPI
 /* eSPI Initialization functions */
 void espi_init(void);
 /* eSPI reset assert/de-assert interrupt */
 void espi_espirst_handler(void);
-#else
 /* LPC PLTRST assert/de-assert interrupt */
 void lpc_lreset_pltrst_handler(void);
-#endif
 #endif /* __CROS_EC_LPC_CHIP_H */