diff options
author | Leifu Zhao <leifu.zhao@intel.com> | 2020-02-14 10:20:52 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-02-27 00:29:03 +0000 |
commit | e225427d2a04449d65fbae72932caa8270f182c7 (patch) | |
tree | 3eda9062fb68d8d243aee5969a430cd84d8a57ae | |
parent | af07a29b0ab75abc03d6d6387257981bd10447b2 (diff) | |
download | chrome-ec-e225427d2a04449d65fbae72932caa8270f182c7.tar.gz |
ish: infrastructure changes to support ish5.4 PM
Infrastructure related changes to support enabling power management
for ish5.4 on tgl rvp platform.
BUG=b:149238813
BRANCH=none
TEST=ISH can successfully enter into D0i1/D0i2/D0i3 on tgl rvp.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: I50b6f1a4fe9c14f9479af2a2a438ec7395ec27a1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2056149
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
-rw-r--r-- | chip/ish/build.mk | 1 | ||||
-rw-r--r-- | chip/ish/config_chip.h | 6 | ||||
-rw-r--r-- | chip/ish/dma.c | 6 | ||||
-rw-r--r-- | chip/ish/registers.h | 50 | ||||
-rw-r--r-- | chip/ish/reset_prep_wr.c | 40 | ||||
-rw-r--r-- | chip/ish/system.c | 31 | ||||
-rw-r--r-- | chip/ish/uart.c | 17 | ||||
-rw-r--r-- | core/minute-ia/interrupts.c | 4 | ||||
-rw-r--r-- | include/config.h | 6 |
9 files changed, 114 insertions, 47 deletions
diff --git a/chip/ish/build.mk b/chip/ish/build.mk index bce9322184..34eace379e 100644 --- a/chip/ish/build.mk +++ b/chip/ish/build.mk @@ -18,7 +18,6 @@ endif # Required chip modules chip-y+=clock.o gpio.o system.o hwtimer.o uart.o flash.o ish_persistent_data.o -chip-$(CHIP_VARIANT_ISH5P4)+=reset_prep_wr.o chip-$(CONFIG_I2C)+=i2c.o chip-$(CONFIG_WATCHDOG)+=watchdog.o chip-$(CONFIG_HOSTCMD_HECI)+=host_command_heci.o diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h index b4dea95767..4c884d00cc 100644 --- a/chip/ish/config_chip.h +++ b/chip/ish/config_chip.h @@ -41,7 +41,11 @@ #define CONFIG_RAM_BASE 0xFF000000 #endif #define CONFIG_RAM_SIZE 0x000A0000 -#define CONFIG_RAM_BANK_SIZE 0x00008000 +#ifdef CHIP_VARIANT_ISH5P4 +#define CONFIG_RAM_BANK_SIZE 0x00010000 +#else +#define CONFIG_RAM_BANK_SIZE 0x00008000 +#endif #if defined(CHIP_FAMILY_ISH3) /* On ISH3, there is no separate AON memory; use last 4KB of SRAM */ diff --git a/chip/ish/dma.c b/chip/ish/dma.c index a409dc6ad3..b9744fd234 100644 --- a/chip/ish/dma.c +++ b/chip/ish/dma.c @@ -37,9 +37,11 @@ static int dma_poll(uint32_t addr, uint32_t expected, uint32_t mask) void ish_dma_ocp_timeout_disable(void) { - uint32_t ctrl = OCP_AGENT_CONTROL; + if (!IS_ENABLED(CONFIG_ISH_NEW_PM)) { + uint32_t ctrl = OCP_AGENT_CONTROL; - OCP_AGENT_CONTROL = ctrl & OCP_RESPONSE_TO_DISABLE; + OCP_AGENT_CONTROL = ctrl & OCP_RESPONSE_TO_DISABLE; + } } static inline uint32_t interrupt_lock(void) diff --git a/chip/ish/registers.h b/chip/ish/registers.h index d4ac2ea47a..b8bca3e975 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -40,7 +40,7 @@ enum ish_i2c_port { #define ISH_GPIO_BASE 0x00100000 #define ISH_PMU_BASE 0x04200000 #define ISH_OCP_BASE 0xFFFFFFFF -#define ISH_MISC_BASE 0xFFFFFFFF +#define ISH_MISC_BASE 0x04400000 #define ISH_DMA_BASE 0x10100000 #define ISH_CCU_BASE 0x04300000 #define ISH_IPC_BASE 0x04100000 @@ -186,6 +186,7 @@ enum ish_i2c_port { /* PMU Registers */ #define PMU_SRAM_PG_EN REG32(ISH_PMU_BASE + 0x0) +#ifndef CHIP_VARIANT_ISH5P4 #define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x4) #define PMU_D3_BIT_SET BIT(0) #define PMU_D3_BIT_RISING_EDGE_STATUS BIT(1) @@ -197,12 +198,28 @@ enum ish_i2c_port { #define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(7) #define PMU_BME_BIT_RISING_EDGE_MASK BIT(8) #define PMU_BME_BIT_FALLING_EDGE_MASK BIT(9) +#else +#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x100) +#define PMU_D3_BIT_SET BIT(16) +#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(17) +#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(18) +#define PMU_D3_BIT_RISING_EDGE_MASK BIT(19) +#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(20) +#define PMU_BME_BIT_SET BIT(24) +#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(25) +#define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(26) +#define PMU_BME_BIT_RISING_EDGE_MASK BIT(27) +#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(28) +#endif + #define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c) #define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */ #define PMU_VNN_REQ_ACK REG32(ISH_PMU_BASE + 0x40) #define PMU_VNN_REQ_ACK_STATUS BIT(0) /* VNN req and ack status */ +#define PMU_VNNAON_RED REG32(ISH_PMU_BASE + 0x58) + #define PMU_RST_PREP REG32(ISH_PMU_BASE + 0x5c) #define PMU_RST_PREP_GET BIT(0) #define PMU_RST_PREP_AVAIL BIT(1) @@ -218,14 +235,24 @@ enum ish_i2c_port { /* MISC registers */ #define MISC_REG_BASE ISH_MISC_BASE +#define DMA_REG_BASE ISH_DMA_BASE +#ifndef CHIP_VARIANT_ISH5P4 #define MISC_CHID_CFG_REG REG32(MISC_REG_BASE + 0x40) #define MISC_DMA_CTL_REG(ch) REG32(MISC_REG_BASE + (4 * (ch))) #define MISC_SRC_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x20 + (4 * (ch))) #define MISC_DST_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x80 + (4 * (ch))) #define MISC_ISH_ECC_ERR_SRESP REG32(MISC_REG_BASE + 0x94) +#else +#define DMA_MISC_OFFSET 0x1000 +#define DMA_MISC_BASE (DMA_REG_BASE + DMA_MISC_OFFSET) +#define MISC_CHID_CFG_REG REG32(DMA_MISC_BASE + 0x400) +#define MISC_DMA_CTL_REG(ch) REG32(DMA_MISC_BASE + (4 * (ch))) +#define MISC_SRC_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x100 + (4 * (ch))) +#define MISC_DST_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x200 + (4 * (ch))) +#define MISC_ISH_ECC_ERR_SRESP REG32(DMA_MISC_BASE + 0x404) +#endif /* DMA registers */ -#define DMA_REG_BASE ISH_DMA_BASE #define DMA_CH_REGS_SIZE 0x58 #define DMA_CLR_BLOCK_REG REG32(DMA_REG_BASE + 0x340) #define DMA_CLR_ERR_REG REG32(DMA_REG_BASE + 0x358) @@ -286,10 +313,24 @@ enum ish_i2c_port { /* CCU Registers */ #define CCU_TCG_EN REG32(ISH_CCU_BASE + 0x0) #define CCU_BCG_EN REG32(ISH_CCU_BASE + 0x4) +#ifndef CHIP_VARIANT_ISH5P4 #define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x8) #define CCU_RST_HST REG32(ISH_CCU_BASE + 0x34) /* Reset history */ #define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x38) #define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x3c) +#else +#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x7c) +#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x3c) /* Reset history */ +#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x40) +#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x44) +#endif +#define CCU_BCG_MIA REG32(ISH_CCU_BASE + 0x4) +#define CCU_BCG_UART REG32(ISH_CCU_BASE + 0x8) +#define CCU_BCG_I2C REG32(ISH_CCU_BASE + 0xc) +#define CCU_BCG_SPI REG32(ISH_CCU_BASE + 0x10) +#define CCU_BCG_GPIO REG32(ISH_CCU_BASE + 0x14) +#define CCU_BCG_DMA REG32(ISH_CCU_BASE + 0x28) +#define CCU_AONCG_EN REG32(ISH_CCU_BASE + 0xdc) #define CCU_BCG_BIT_MIA BIT(0) #define CCU_BCG_BIT_DMA BIT(1) #define CCU_BCG_BIT_I2C0 BIT(2) @@ -325,6 +366,7 @@ enum ish_i2c_port { #define SEC_OFFSET 0x0 #endif #define ISH_RST_REG REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44) +#define IPC_PIMR_CIM_SEC (ISH_IPC_BASE + SEC_OFFSET + 0x10) /* IOAPIC registers */ #define IOAPIC_IDX REG32(ISH_IOAPIC_BASE + 0x0) @@ -362,7 +404,11 @@ enum ish_i2c_port { #define LAPIC_ICR_REG REG32(ISH_LAPIC_BASE + 0x300) /* SRAM control registers */ +#ifndef CHIP_VARIANT_ISH5P4 #define ISH_SRAM_CTRL_BASE 0x00500000 +#else +#define ISH_SRAM_CTRL_BASE 0x10500000 +#endif #define ISH_SRAM_CTRL_CSFGR REG32(ISH_SRAM_CTRL_BASE + 0x00) #define ISH_SRAM_CTRL_INTR REG32(ISH_SRAM_CTRL_BASE + 0x04) #define ISH_SRAM_CTRL_INTR_MASK REG32(ISH_SRAM_CTRL_BASE + 0x08) diff --git a/chip/ish/reset_prep_wr.c b/chip/ish/reset_prep_wr.c deleted file mode 100644 index c192fb3723..0000000000 --- a/chip/ish/reset_prep_wr.c +++ /dev/null @@ -1,40 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Workaround for ISH5.4 reset prep handling before full PM is enabled */ -#include "common.h" -#include "hooks.h" -#include "interrupts.h" -#include "registers.h" -#include "system.h" -#include "task.h" - -/* - * IRQ fires when we receive a RESET_PREP message from AP. This happens at S0 - * entry. - */ -static void reset_prep_wr_isr(void) -{ - system_reset(SYSTEM_RESET_HARD); -} -DECLARE_IRQ(ISH_RESET_PREP_IRQ, reset_prep_wr_isr); - -void reset_prep_init(void) -{ - /* Clear reset bit */ - ISH_RST_REG = 0; - - /* Clear reset history register from previous boot. */ - CCU_RST_HST = CCU_RST_HST; - /* Unmask reset prep avail interrupt mask */ - PMU_RST_PREP = 0; - /* Clear TCG Enable, no trunk level clock gating*/ - CCU_TCG_ENABLE = 0; - /* Clear BCG Enable, no block level clock gating*/ - CCU_BCG_ENABLE = 0; - - task_enable_irq(ISH_RESET_PREP_IRQ); -} -DECLARE_HOOK(HOOK_INIT, reset_prep_init, HOOK_PRIO_DEFAULT); diff --git a/chip/ish/system.c b/chip/ish/system.c index 280bf57fa4..c26026dcb8 100644 --- a/chip/ish/system.c +++ b/chip/ish/system.c @@ -175,6 +175,37 @@ void system_set_image_copy(enum system_image_copy_t copy) { } +#define HBW_FABRIC_BASE 0x10000000 +#define PER0_FABRIC_BASE 0x04000000 +#define AGENT_STS 0x28 +#define ERROR_LOG 0x58 + +static uint16_t hbw_ia_offset[] = { + 0x1000, + 0x3400, + 0x3800, + 0x5000, + 0x5800, + 0x6000 +}; + +static inline void clear_register(uint32_t reg) +{ + REG32(reg) = REG32(reg); +} + +void clear_fabric_error(void) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(hbw_ia_offset); i++) { + clear_register(HBW_FABRIC_BASE + hbw_ia_offset[i] + AGENT_STS); + clear_register(HBW_FABRIC_BASE + hbw_ia_offset[i] + ERROR_LOG); + } + clear_register(PER0_FABRIC_BASE + 0x1000 + AGENT_STS); + clear_register(PER0_FABRIC_BASE + 0x1000 + ERROR_LOG); +} + static __maybe_unused void fabric_isr(void) { /** diff --git a/chip/ish/uart.c b/chip/ish/uart.c index 93df2c6504..d958dc94c5 100644 --- a/chip/ish/uart.c +++ b/chip/ish/uart.c @@ -205,6 +205,23 @@ static void uart_hw_init(enum UART_PORT id) IER(ctx->id) = IER_RECV; } +void uart_port_restore(void) +{ + uart_hw_init(ISH_DEBUG_UART); +} + +void uart_to_idle(void) +{ + int id; + + for (id = 0; id < UART_DEVICES; id++) { + LCR(id) = 0x80; + DLL(id) = 0x1; + DLH(id) = 0x0; + LCR(id) = 0x0; + } +} + static void uart_stop_hw(enum UART_PORT id) { int i; diff --git a/core/minute-ia/interrupts.c b/core/minute-ia/interrupts.c index 714fde239e..3dbb4f85fe 100644 --- a/core/minute-ia/interrupts.c +++ b/core/minute-ia/interrupts.c @@ -151,7 +151,7 @@ static const irq_desc_t system_irqs[] = { LEVEL_INTR(ISH_HPET_TIMER1_IRQ, ISH_HPET_TIMER1_VEC), LEVEL_INTR(ISH_DEBUG_UART_IRQ, ISH_DEBUG_UART_VEC), LEVEL_INTR(ISH_FABRIC_IRQ, ISH_FABRIC_VEC), -#if defined(CONFIG_ISH_PM_RESET_PREP) || defined(CHIP_VARIANT_ISH5P4) +#ifdef CONFIG_ISH_PM_RESET_PREP LEVEL_INTR(ISH_RESET_PREP_IRQ, ISH_RESET_PREP_VEC), #endif #ifdef CONFIG_ISH_PM_D0I1 @@ -159,10 +159,12 @@ static const irq_desc_t system_irqs[] = { #endif #ifdef CONFIG_ISH_PM_D3 LEVEL_INTR(ISH_D3_RISE_IRQ, ISH_D3_RISE_VEC), +#ifndef CONFIG_ISH_NEW_PM LEVEL_INTR(ISH_D3_FALL_IRQ, ISH_D3_FALL_VEC), LEVEL_INTR(ISH_BME_RISE_IRQ, ISH_BME_RISE_VEC), LEVEL_INTR(ISH_BME_FALL_IRQ, ISH_BME_FALL_VEC) #endif +#endif }; /** diff --git a/include/config.h b/include/config.h index b289658130..59828ca716 100644 --- a/include/config.h +++ b/include/config.h @@ -4569,6 +4569,12 @@ #undef CONFIG_ISH_D0I3_MIN_USEC /* + * Define the following if the new specific power management processing + * after ISH 5.4 is used. + */ +#undef CONFIG_ISH_NEW_PM + +/* * Define the following in order to perform power management reset * prep IRQ setup when entering a new state */ |