TCPCI: Add PPC driver for generic TCPC

This CL adds a PPC driver for TCPCI conformant TCPCs.

On some boards, EC indirectly controls PPCs through TCPCs which supports
TCPCI. This is a PPC driver for such configurations.

BUG=b:257320026,b:272821227
BRANCH=None
TEST=Agah

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I4eda5f6dfc398723b223c51de5c58aa7a5d45fd6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4455301
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Tarun Tuli <taruntuli@google.com>

5 files changed, 114 insertions, 3 deletions

diff --git a/driver/build.mk b/driver/build.mk
index ba8078b11e..a897bc83a0 100644
--- a/driver/build.mk
+++ b/driver/build.mk
@@ -232,6 +232,7 @@ endif
 driver-$(CONFIG_USBC_PPC_SYV682X)+=ppc/syv682x.o
 driver-$(CONFIG_USBC_PPC_NX20P3483)+=ppc/nx20p348x.o
 driver-$(CONFIG_USBC_PPC_KTU1125)+=ppc/ktu1125.o
+driver-$(CONFIG_USBC_PPC_TCPCI)+=ppc/tcpci_ppc.o
 
 # Switchcap
 driver-$(CONFIG_LN9310)+=ln9310.o
diff --git a/driver/ppc/tcpci_ppc.c b/driver/ppc/tcpci_ppc.c
new file mode 100644
index 0000000000..055c7f3048
--- /dev/null
+++ b/driver/ppc/tcpci_ppc.c
@@ -0,0 +1,91 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB-C Power Path Controller via TCPCI conformant TCPC */
+
+#include "atomic.h"
+#include "common.h"
+#include "console.h"
+#include "driver/tcpm/tcpci.h"
+#include "usbc_ppc.h"
+
+#define TCPCI_PPC_FLAGS_SOURCE_ENABLED BIT(0)
+
+static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static int tcpci_ppc_is_sourcing_vbus(int port)
+{
+	return (flags[port] & TCPCI_PPC_FLAGS_SOURCE_ENABLED);
+}
+
+static int tcpci_ppc_vbus_source_enable(int port, int enable)
+{
+	RETURN_ERROR(tcpci_tcpm_set_src_ctrl(port, enable));
+
+	if (enable)
+		atomic_or(&flags[port], TCPCI_PPC_FLAGS_SOURCE_ENABLED);
+	else
+		atomic_clear_bits(&flags[port], TCPCI_PPC_FLAGS_SOURCE_ENABLED);
+
+	/*
+	 * Since the VBUS state could be changing here, need to wake the
+	 * USB_CHG_N task so that BC 1.2 detection will be triggered.
+	 */
+	if (IS_ENABLED(CONFIG_USB_CHARGER) &&
+	    IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_PPC))
+		usb_charger_vbus_change(port, enable);
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+static int tcpci_is_vbus_present(int port)
+{
+	int status;
+
+	if (tcpci_tcpm_get_power_status(port, &status))
+		return 0;
+
+	return !!(status & TCPC_REG_POWER_STATUS_VBUS_PRES);
+}
+#endif
+
+static int tcpci_ppc_discharge_vbus(int port, int enable)
+{
+	tcpci_tcpc_discharge_vbus(port, enable);
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USBC_PPC_POLARITY
+static int tcpci_ppc_set_polarity(int port, int polarity)
+{
+	return tcpci_tcpm_set_polarity(port, polarity);
+}
+#endif
+
+static int tcpci_ppc_init(int port)
+{
+	atomic_clear(&flags[port]);
+
+	return EC_SUCCESS;
+}
+
+const struct ppc_drv tcpci_ppc_drv = {
+	.init = &tcpci_ppc_init,
+	.is_sourcing_vbus = tcpci_ppc_is_sourcing_vbus,
+	.vbus_sink_enable = tcpci_tcpm_set_snk_ctrl,
+	.vbus_source_enable = tcpci_ppc_vbus_source_enable,
+
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+	.is_vbus_present = tcpci_is_vbus_present,
+#endif
+
+	.discharge_vbus = tcpci_ppc_discharge_vbus,
+
+#ifdef CONFIG_USBC_PPC_POLARITY
+	.set_polarity = tcpci_ppc_set_polarity,
+#endif
+};
diff --git a/driver/ppc/tcpci_ppc.h b/driver/ppc/tcpci_ppc.h
new file mode 100644
index 0000000000..0afe2d245e
--- /dev/null
+++ b/driver/ppc/tcpci_ppc.h
@@ -0,0 +1,8 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB-C Power Path Controller via TCPCI conformant TCPC */
+
+extern const struct ppc_drv tcpci_ppc_drv;
diff --git a/include/config.h b/include/config.h
index a7b211699e..3279cbc821 100644
--- a/include/config.h
+++ b/include/config.h
@@ -5206,6 +5206,7 @@
 #undef CONFIG_USBC_PPC_SN5S330
 #undef CONFIG_USBC_PPC_SYV682C
 #undef CONFIG_USBC_PPC_SYV682X
+#undef CONFIG_USBC_PPC_TCPCI
 
 /*
  * NX20P348x 5V SRC RCP trigger level at 10mV. Define to enable 5V SRC RCP
@@ -6244,13 +6245,13 @@
 /*****************************************************************************/
 /* Define CONFIG_USBC_PPC if board has a USB Type-C Power Path Controller. */
 #if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_NX20P3483) || \
-	defined(CONFIG_USBC_PPC_SN5S330)
+	defined(CONFIG_USBC_PPC_SN5S330) || defined(CONFIG_USBC_PPC_TCPCI)
 #define CONFIG_USBC_PPC
 #endif /* "has a PPC" */
 
 /* Following chips use Power Path Control information from TCPC chip */
 #if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_NX20P3481) || \
-	defined(CONFIG_USBC_PPC_NX20P3483)
+	defined(CONFIG_USBC_PPC_NX20P3483) || defined(CONFIG_USBC_PPC_TCPCI)
 #define CONFIG_USB_PD_PPC
 #endif
 
@@ -6302,7 +6303,8 @@
 	defined(CONFIG_USBC_PPC_NX20P3483) ||                                 \
 	defined(CONFIG_USBC_PPC_SN5S330) ||                                   \
 	defined(CONFIG_USBC_PPC_SYV682X) || defined(CONFIG_CHARGER_SM5803) || \
-	defined(CONFIG_USB_PD_TCPM_TCPCI)
+	defined(CONFIG_USB_PD_TCPM_TCPCI) ||                                  \
+	defined(CONFIG_USB_PD_TCPM_ANX7406)
 #define CONFIG_USBC_OCP
 #endif
 
diff --git a/zephyr/Kconfig.ppc b/zephyr/Kconfig.ppc
index 85cae5b664..142e7cf12e 100644
--- a/zephyr/Kconfig.ppc
+++ b/zephyr/Kconfig.ppc
@@ -60,6 +60,15 @@ config PLATFORM_EC_USBC_PPC_AOZ1380
 	  provide all the functionality and protection needed for sourcing
 	  and sinking current through a USB Type-C port with PD capability.
 
+config PLATFORM_EC_USBC_PPC_TCPCI
+	bool "USB-C TCPCI PD Sink and Source Protection Switch"
+	select PLATFORM_EC_USBC_OCP
+	help
+	  A TCPC which supports TCPCI integrates two power switches and control
+	  circuitry to provide the functionality and protection needed for
+	  sourcing and sinking current through a USB Type-C port with PD
+	  capability.
+
 config PLATFORM_EC_USBC_PPC_RT1718S
 	bool "Richtek RT1718S TCPC/PPC"
 	select PLATFORM_EC_USB_PD_TCPM_RT1718S