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author | Jack Rosenthal <jrosenth@chromium.org> | 2021-11-04 12:11:58 -0600 |
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committer | Commit Bot <commit-bot@chromium.org> | 2021-11-05 04:22:34 +0000 |
commit | 252457d4b21f46889eebad61d4c0a65331919cec (patch) | |
tree | 01856c4d31d710b20e85a74c8d7b5836e35c3b98 /baseboard/intelrvp/README.md | |
parent | 08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff) | |
download | chrome-ec-stabilize-14526.84.B-ish.tar.gz |
ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'baseboard/intelrvp/README.md')
-rw-r--r-- | baseboard/intelrvp/README.md | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/baseboard/intelrvp/README.md b/baseboard/intelrvp/README.md deleted file mode 100644 index 39286e130d..0000000000 --- a/baseboard/intelrvp/README.md +++ /dev/null @@ -1,53 +0,0 @@ -This folder is for the baseboard for the board specific files which use Intel -Reference Validation Platform (RVP) for developing the EC and other peripherals -which can be hooked on EC or RVP. - -This baseboard follows the Intel Modular Embedded Controller Card (MECC) -specification for pinout and these pin definitions remain same on all the RVPs. -Chrome MECC spec is standardized for Icelake and successor RVPs hence this -baseboard code is applicable to Icelake and its successors only. - -Following hardware features are supported on MECC header by RVP and can be -validated by software by MECC. - -## MECC version 0.9 features - -1. Power to MECC is provided by RVP (battery + DC Jack + Type C) -2. Power control pins for Intel SOC are added -3. Servo V2 header need to be added by MECC -4. Google H1 chip need to be added by MECC (optional for EC vendors) -5. 2 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer) -6. 6 Temperature sensors -7. 4 ADC -8. 4 I2C Channels -9. 1 Fan control - -## MECC version 1.0 features - -1. Power to MECC is provided by RVP (battery + DC Jack + Type C) -2. Power control pins for Intel SOC are added -3. Servo V2 header need to be added by MECC -4. Google H1 chip need to be added by MECC (optional for EC vendors) -5. 4 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer) as Add In Card (AIC) on - RVP -6. Optional 2 Type-C port routed to MECC for integrated TCPC support -7. 6 I2C Channels -8. 2 SMLINK Channels -9. 2 I3C channels - -## MECC version 1.1 features - -1. Power to MECC is provided by RVP (battery + DC Jack + Type C) -2. Power control pins for Intel SOC are added -3. Servo V2 header is added on RVP as an AIC -4. Google H1 chip is added on RVP as an AIC -5. 4 Type-C port support (SRC/SNK/MUX/Rerimer) as an (AIC) -6. Optional 2 Type-C port routed to MECC for integrated TCPC support -7. 6 I2C Channels -8. 2 SMLINK Channels -9. 2 I3C channels -10. 1 Fan control -11. 4 ADC based temperature sensors -12. PECI control -13. I2C based Keyboard is added on RVP as an AIC -14. Both Google & Intel CCD support is added on RVP on Type-C port 0 |