ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

24 files changed, 0 insertions, 2601 deletions

diff --git a/baseboard/intelrvp/README.md b/baseboard/intelrvp/README.md
deleted file mode 100644
index 39286e130d..0000000000
--- a/baseboard/intelrvp/README.md
+++ /dev/null
@@ -1,53 +0,0 @@
-This folder is for the baseboard for the board specific files which use Intel
-Reference Validation Platform (RVP) for developing the EC and other peripherals
-which can be hooked on EC or RVP.
-
-This baseboard follows the Intel Modular Embedded Controller Card (MECC)
-specification for pinout and these pin definitions remain same on all the RVPs.
-Chrome MECC spec is standardized for Icelake and successor RVPs hence this
-baseboard code is applicable to Icelake and its successors only.
-
-Following hardware features are supported on MECC header by RVP and can be
-validated by software by MECC.
-
-## MECC version 0.9 features
-
-1.  Power to MECC is provided by RVP (battery + DC Jack + Type C)
-2.  Power control pins for Intel SOC are added
-3.  Servo V2 header need to be added by MECC
-4.  Google H1 chip need to be added by MECC (optional for EC vendors)
-5.  2 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer)
-6.  6 Temperature sensors
-7.  4 ADC
-8.  4 I2C Channels
-9.  1 Fan control
-
-## MECC version 1.0 features
-
-1.  Power to MECC is provided by RVP (battery + DC Jack + Type C)
-2.  Power control pins for Intel SOC are added
-3.  Servo V2 header need to be added by MECC
-4.  Google H1 chip need to be added by MECC (optional for EC vendors)
-5.  4 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer) as Add In Card (AIC) on
-    RVP
-6.  Optional 2 Type-C port routed to MECC for integrated TCPC support
-7.  6 I2C Channels
-8.  2 SMLINK Channels
-9.  2 I3C channels
-
-## MECC version 1.1 features
-
-1.  Power to MECC is provided by RVP (battery + DC Jack + Type C)
-2.  Power control pins for Intel SOC are added
-3.  Servo V2 header is added on RVP as an AIC
-4.  Google H1 chip is added on RVP as an AIC
-5.  4 Type-C port support (SRC/SNK/MUX/Rerimer) as an (AIC)
-6.  Optional 2 Type-C port routed to MECC for integrated TCPC support
-7.  6 I2C Channels
-8.  2 SMLINK Channels
-9.  2 I3C channels
-10. 1 Fan control
-11. 4 ADC based temperature sensors
-12. PECI control
-13. I2C based Keyboard is added on RVP as an AIC
-14. Both Google & Intel CCD support is added on RVP on Type-C port 0
diff --git a/baseboard/intelrvp/adlrvp.c b/baseboard/intelrvp/adlrvp.c
deleted file mode 100644
index 78f4b3613a..0000000000
--- a/baseboard/intelrvp/adlrvp.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADLRVP board-specific common configuration */
-
-#include "charger.h"
-#include "common.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "isl9241.h"
-#include "pca9675.h"
-#include "power/icelake.h"
-#include "sn5s330.h"
-#include "system.h"
-#include "task.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
-
-/* TCPC AIC GPIO Configuration */
-const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = {
-	[TYPE_C_PORT_0] = {
-		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P0,
-		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P0,
-		.ppc_intr_handler = sn5s330_interrupt,
-	},
-#if defined(HAS_TASK_PD_C1)
-	[TYPE_C_PORT_1] = {
-		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P1,
-		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P1,
-		.ppc_intr_handler = sn5s330_interrupt,
-	},
-#endif
-#if defined(HAS_TASK_PD_C2)
-	[TYPE_C_PORT_2] = {
-		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P2,
-		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P2,
-		.ppc_intr_handler = sn5s330_interrupt,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[TYPE_C_PORT_3] = {
-		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P3,
-		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P3,
-		.ppc_intr_handler = sn5s330_interrupt,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* USB-C PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[TYPE_C_PORT_0] = {
-		.i2c_port = I2C_PORT_TYPEC_0,
-		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
-		.drv = &sn5s330_drv,
-	},
-#if defined(HAS_TASK_PD_C1)
-	[TYPE_C_PORT_1] = {
-		.i2c_port = I2C_PORT_TYPEC_1,
-		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
-		.drv = &sn5s330_drv
-	},
-#endif
-#if defined(HAS_TASK_PD_C2)
-	[TYPE_C_PORT_2] = {
-		.i2c_port = I2C_PORT_TYPEC_2,
-		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
-		.drv = &sn5s330_drv,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[TYPE_C_PORT_3] = {
-		.i2c_port = I2C_PORT_TYPEC_3,
-		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
-		.drv = &sn5s330_drv,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USB-C retimer Configuration */
-struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = TYPE_C_PORT_0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-#if defined(HAS_TASK_PD_C1)
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = TYPE_C_PORT_1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-#endif
-#if defined(HAS_TASK_PD_C2)
-struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = TYPE_C_PORT_2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-#endif
-#if defined(HAS_TASK_PD_C3)
-struct usb_mux usbc3_tcss_usb_mux = {
-	.usb_port = TYPE_C_PORT_3,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-#endif
-
-/* USB muxes Configuration */
-struct usb_mux usb_muxes[] = {
-	[TYPE_C_PORT_0] = {
-		.usb_port = TYPE_C_PORT_0,
-		.next_mux = &usbc0_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_TYPEC_0,
-		.i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR,
-	},
-#if defined(HAS_TASK_PD_C1)
-	[TYPE_C_PORT_1] = {
-		.usb_port = TYPE_C_PORT_1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_TYPEC_1,
-		.i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR,
-	},
-#endif
-#if defined(HAS_TASK_PD_C2)
-	[TYPE_C_PORT_2] = {
-		.usb_port = TYPE_C_PORT_2,
-		.next_mux = &usbc2_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_TYPEC_2,
-		.i2c_addr_flags = I2C_PORT2_BB_RETIMER_ADDR,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[TYPE_C_PORT_3] = {
-		.usb_port = TYPE_C_PORT_3,
-		.next_mux = &usbc3_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_TYPEC_3,
-		.i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* USB Mux Configuration for Soc side BB-Retimers for Dual retimer config */
-struct usb_mux soc_side_bb_retimer0_usb_mux = {
-	.usb_port = TYPE_C_PORT_0,
-	.next_mux = &usbc0_tcss_usb_mux,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_TYPEC_0,
-	.i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR,
-};
-
-#if defined(HAS_TASK_PD_C1)
-struct usb_mux soc_side_bb_retimer1_usb_mux = {
-	.usb_port = TYPE_C_PORT_1,
-	.next_mux = &usbc1_tcss_usb_mux,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_TYPEC_1,
-	.i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR,
-};
-#endif
-
-const struct bb_usb_control bb_controls[] = {
-	[TYPE_C_PORT_0] = {
-		.retimer_rst_gpio = IOEX_USB_C0_BB_RETIMER_RST,
-		.usb_ls_en_gpio = IOEX_USB_C0_BB_RETIMER_LS_EN,
-	},
-#if defined(HAS_TASK_PD_C1)
-	[TYPE_C_PORT_1] = {
-		.retimer_rst_gpio = IOEX_USB_C1_BB_RETIMER_RST,
-		.usb_ls_en_gpio = IOEX_USB_C1_BB_RETIMER_LS_EN,
-	},
-#endif
-#if defined(HAS_TASK_PD_C2)
-	[TYPE_C_PORT_2] = {
-		.retimer_rst_gpio = IOEX_USB_C2_BB_RETIMER_RST,
-		.usb_ls_en_gpio = IOEX_USB_C2_BB_RETIMER_LS_EN,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[TYPE_C_PORT_3] = {
-		.retimer_rst_gpio = IOEX_USB_C3_BB_RETIMER_RST,
-		.usb_ls_en_gpio = IOEX_USB_C3_BB_RETIMER_LS_EN,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* Cache BB retimer power state */
-static bool cache_bb_enable[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Each TCPC have corresponding IO expander and are available in pair */
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_PCA9675] = {
-		.i2c_host_port = I2C_PORT_TYPEC_0,
-		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
-		.drv = &pca9675_ioexpander_drv,
-	},
-	[IOEX_C1_PCA9675] = {
-		.i2c_host_port = I2C_PORT_TYPEC_1,
-		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
-		.drv = &pca9675_ioexpander_drv,
-	},
-#if defined(HAS_TASK_PD_C2)
-	[IOEX_C2_PCA9675] = {
-		.i2c_host_port = I2C_PORT_TYPEC_2,
-		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
-		.drv = &pca9675_ioexpander_drv,
-	},
-	[IOEX_C3_PCA9675] = {
-		.i2c_host_port = I2C_PORT_TYPEC_3,
-		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
-		.drv = &pca9675_ioexpander_drv,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Port 0 & 1 and 2 & 3 share same line for over current indication */
-#if defined(HAS_TASK_PD_C2)
-	enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ?
-				IOEX_USB_C0_C1_OC : IOEX_USB_C2_C3_OC;
-#else
-	enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC;
-#endif
-
-	/* Overcurrent indication is active low signal */
-	ioex_set_level(oc_signal, is_overcurrented ? 0 : 1);
-}
-
-__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
-{
-	/*
-	 * ADL-P-DDR5 RVP SKU has cascaded retimer topology.
-	 * Ports with cascaded retimers share common load switch and reset pin
-	 * hence no need to set the power state again if the 1st retimer's power
-	 * status has already changed.
-	 */
-	if (cache_bb_enable[me->usb_port] == enable)
-		return EC_SUCCESS;
-
-	cache_bb_enable[me->usb_port] = enable;
-
-	/* Handle retimer's power domain.*/
-	if (enable) {
-		ioex_set_level(bb_controls[me->usb_port].usb_ls_en_gpio, 1);
-
-		/*
-		 * minimum time from VCC to RESET_N de-assertion is 100us
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		msleep(1);
-		ioex_set_level(bb_controls[me->usb_port].retimer_rst_gpio, 1);
-
-		/*
-		 * Allow 1ms time for the retimer to power up lc_domain
-		 * which powers I2C controller within retimer
-		 */
-		msleep(1);
-
-	} else {
-		ioex_set_level(bb_controls[me->usb_port].retimer_rst_gpio, 0);
-		msleep(1);
-		ioex_set_level(bb_controls[me->usb_port].usb_ls_en_gpio, 0);
-	}
-	return EC_SUCCESS;
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	int ccd_intr_level = gpio_get_level(GPIO_CCD_MODE_ODL);
-
-	if (ccd_intr_level) {
-		/* Default set the SBU lines to AUX mode on TCPC-AIC */
-		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_1, 0);
-		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_0, 0);
-	} else {
-		/* Set the SBU lines to CCD mode on TCPC-AIC */
-		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_1, 1);
-		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_0, 0);
-	}
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-/* Make sure SBU are routed to CCD or AUX based on CCD status at init */
-DECLARE_HOOK(HOOK_INIT, board_connect_c0_sbu_deferred, HOOK_PRIO_INIT_I2C + 2);
-
-void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
-static void enable_h1_irq(void)
-{
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, enable_h1_irq, HOOK_PRIO_LAST);
-
-static void configure_retimer_usbmux(void)
-{
-	switch (ADL_RVP_BOARD_ID(board_get_version())) {
-	case ADLN_LP5_ERB_SKU_BOARD_ID:
-	case ADLN_LP5_RVP_SKU_BOARD_ID:
-		/* No retimer on Port0 & Port1 */
-		usb_muxes[TYPE_C_PORT_0].driver = NULL;
-#if defined(HAS_TASK_PD_C1)
-		usb_muxes[TYPE_C_PORT_1].driver = NULL;
-#endif
-		break;
-
-	case ADLP_LP5_T4_RVP_SKU_BOARD_ID:
-		/* No retimer on Port-2 */
-#if defined(HAS_TASK_PD_C2)
-		usb_muxes[TYPE_C_PORT_2].driver = NULL;
-#endif
-		break;
-
-	case ADLP_DDR5_RVP_SKU_BOARD_ID:
-		/*
-		 * ADL-P-DDR5 RVP has dual BB-retimers for port0 & port1.
-		 * Change the default usb mux config on runtime to support
-		 * dual retimer topology.
-		 */
-		usb_muxes[TYPE_C_PORT_0].next_mux
-			= &soc_side_bb_retimer0_usb_mux;
-#if defined(HAS_TASK_PD_C1)
-		usb_muxes[TYPE_C_PORT_1].next_mux
-			= &soc_side_bb_retimer1_usb_mux;
-#endif
-		break;
-
-	/* Add additional board SKUs */
-
-	default:
-		break;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, configure_retimer_usbmux, HOOK_PRIO_INIT_I2C + 1);
-
-/******************************************************************************/
-/* PWROK signal configuration */
-/*
- * On ADLRVP, SYS_PWROK_EC is an output controlled by EC and uses ALL_SYS_PWRGD
- * as input.
- */
-const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
-	{
-		.gpio = GPIO_SYS_PWROK_EC,
-		.delay_ms = 3,
-	},
-};
-const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
-	{
-		.gpio = GPIO_SYS_PWROK_EC,
-	},
-};
-const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-/*
- * Returns board information (board id[7:0] and Fab id[15:8]) on success
- * -1 on error.
- */
-__override int board_get_version(void)
-{
-	/* Cache the ADLRVP board ID */
-	static int adlrvp_board_id;
-
-	int port0, port1;
-	int fab_id, board_id, bom_id;
-
-	/* Board ID is already read */
-	if (adlrvp_board_id)
-		return adlrvp_board_id;
-
-	if (ioexpander_read_intelrvp_version(&port0, &port1))
-		return -1;
-	/*
-	 * Port0: bit 0   - BOM ID(2)
-	 *        bit 2:1 - FAB ID(1:0) + 1
-	 * Port1: bit 7:6 - BOM ID(1:0)
-	 *        bit 5:0 - BOARD ID(5:0)
-	 */
-	bom_id = ((port1 & 0xC0) >> 6) | ((port0 & 0x01) << 2);
-	fab_id = ((port0 & 0x06) >> 1) + 1;
-	board_id = port1 & 0x3F;
-
-	CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id);
-
-	adlrvp_board_id = board_id | (fab_id << 8);
-	return adlrvp_board_id;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	bool tbt_usb4 = true;
-
-	switch (ADL_RVP_BOARD_ID(board_get_version())) {
-	case ADLN_LP5_ERB_SKU_BOARD_ID:
-	case ADLN_LP5_RVP_SKU_BOARD_ID:
-		/* No retimer on both ports */
-		tbt_usb4 = false;
-		break;
-
-	case ADLP_LP5_T4_RVP_SKU_BOARD_ID:
-		/* No retimer on Port-2 hence no platform level AUX & LSx mux */
-#if defined(HAS_TASK_PD_C2)
-		if (port == TYPE_C_PORT_2)
-			tbt_usb4 = false;
-#endif
-		break;
-
-	/* Add additional board SKUs */
-	default:
-		break;
-	}
-
-	return tbt_usb4;
-}
diff --git a/baseboard/intelrvp/adlrvp.h b/baseboard/intelrvp/adlrvp.h
deleted file mode 100644
index 31bfc5aded..0000000000
--- a/baseboard/intelrvp/adlrvp.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-RVP specific configuration */
-
-#ifndef __ADLRVP_BOARD_H
-#define __ADLRVP_BOARD_H
-
-/* Temperature sensor */
-#define CONFIG_TEMP_SENSOR
-
-#include "baseboard.h"
-
-/* RVP Board ids */
-#define CONFIG_BOARD_VERSION_GPIO
-#define ADLN_LP5_ERB_SKU_BOARD_ID	0x06
-#define ADLN_LP5_RVP_SKU_BOARD_ID	0x07
-#define ADLP_DDR5_RVP_SKU_BOARD_ID	0x12
-#define ADLP_LP5_T4_RVP_SKU_BOARD_ID	0x13
-#define ADL_RVP_BOARD_ID(id)		((id) & 0x3F)
-
-/* MECC config */
-#define CONFIG_INTEL_RVP_MECC_VERSION_1_0
-
-/* Support early firmware selection */
-#define CONFIG_VBOOT_EFS2
-
-/* Chipset */
-#define CONFIG_CHIPSET_ALDERLAKE
-
-/* USB PD config */
-#if defined(HAS_TASK_PD_C3)
-#define CONFIG_USB_PD_PORT_MAX_COUNT 4
-#elif defined(HAS_TASK_PD_C2)
-#define CONFIG_USB_PD_PORT_MAX_COUNT 3
-#elif defined(HAS_TASK_PD_C1)
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#else
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#endif
-#define CONFIG_USB_MUX_VIRTUAL
-#define PD_MAX_POWER_MW              100000
-
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
-/* TCPC AIC config */
-/* Support NXP PCA9675 I/O expander. */
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_PCA9675
-#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX	0x21
-
-/* DC Jack charge ports */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-#define DEDICATED_CHARGE_PORT CONFIG_USB_PD_PORT_MAX_COUNT
-
-/* PPC */
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define I2C_ADDR_SN5S330_TCPC_AIC_PPC	0x40
-
-/* TCPC */
-#define CONFIG_USB_PD_DISCHARGE
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define I2C_ADDR_FUSB302_TCPC_AIC	0x22
-
-/* Config BB retimer */
-#define CONFIG_USBC_RETIMER_INTEL_BB
-#define CONFIG_USBC_RETIMER_FW_UPDATE
-
-/* Connector side BB retimers */
-#define I2C_PORT0_BB_RETIMER_ADDR	0x56
-#if defined(HAS_TASK_PD_C1)
-#define I2C_PORT1_BB_RETIMER_ADDR	0x57
-#endif
-#if defined(HAS_TASK_PD_C2)
-#define I2C_PORT2_BB_RETIMER_ADDR	0x58
-#endif
-#if defined(HAS_TASK_PD_C3)
-#define I2C_PORT3_BB_RETIMER_ADDR	0x59
-#endif
-
-/* SOC side BB retimers (dual retimer config) */
-#define I2C_PORT0_BB_RETIMER_SOC_ADDR	0x54
-#if defined(HAS_TASK_PD_C1)
-#define I2C_PORT1_BB_RETIMER_SOC_ADDR	0x55
-#endif
-
-/* I2C EEPROM */
-#define I2C_ADDR_EEPROM_FLAGS   0x50
-#define I2C_PORT_EEPROM         I2C_PORT_PCA9555_BOARD_ID_GPIO
-
-/* Enable CBI */
-#define CONFIG_CBI_EEPROM
-
-/* Configure mux at runtime */
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-/* Enable VCONN */
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-/* Enable low power mode */
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Config Fan */
-#define CONFIG_FANS		1
-#define BOARD_FAN_MIN_RPM	3000
-#define BOARD_FAN_MAX_RPM	10000
-
-/* Charger */
-#define CONFIG_CHARGER_ISL9241
-
-/* Port 80 */
-#define PORT80_I2C_ADDR		MAX695X_I2C_ADDR1_FLAGS
-
-/* Board Id */
-#define I2C_ADDR_PCA9555_BOARD_ID_GPIO	0x22
-
-/*
- * Frequent watchdog timer resets are seen, with the
- * increase in number of type-c ports. So increase
- * the timer value to support more type-c ports.
- */
-#ifdef VARIANT_INTELRVP_EC_IT8320
-#if defined(HAS_TASK_PD_C2) && defined(HAS_TASK_PD_C3)
-#undef CONFIG_WATCHDOG_PERIOD_MS
-#define CONFIG_WATCHDOG_PERIOD_MS 4000
-#endif
-#endif
-
-/*
- * Enable support for battery hostcmd, supporting longer strings.
- * Support for EC_CMD_BATTERY_GET_STATIC version 1.
- */
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT	1
-#define CONFIG_HOSTCMD_BATTERY_V2
-
-#ifndef __ASSEMBLER__
-
-enum adlrvp_charge_ports {
-	TYPE_C_PORT_0,
-#if defined(HAS_TASK_PD_C1)
-	TYPE_C_PORT_1,
-#endif
-#if defined(HAS_TASK_PD_C2)
-	TYPE_C_PORT_2,
-#endif
-#if defined(HAS_TASK_PD_C3)
-	TYPE_C_PORT_3,
-#endif
-};
-
-/*
- * Each Type-C add in card has two I/O expanders hence even if one Type-C port
- * is enabled other I/O expander is available for usage.
- */
-enum ioex_port {
-	IOEX_C0_PCA9675,
-	IOEX_C1_PCA9675,
-#if defined(HAS_TASK_PD_C2)
-	IOEX_C2_PCA9675,
-	IOEX_C3_PCA9675,
-#endif
-	IOEX_PORT_COUNT
-};
-#define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT
-
-enum battery_type {
-	BATTERY_GETAC_SMP_HHP_408,
-	BATTERY_TYPE_COUNT,
-};
-
-void espi_reset_pin_asserted_interrupt(enum gpio_signal signal);
-void extpower_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-void tcpc_alert_event(enum gpio_signal signal);
-void board_connect_c0_sbu(enum gpio_signal s);
-int board_get_version(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __ADLRVP_BOARD_H */
diff --git a/baseboard/intelrvp/adlrvp_battery2s.c b/baseboard/intelrvp/adlrvp_battery2s.c
deleted file mode 100644
index bc61b407a0..0000000000
--- a/baseboard/intelrvp/adlrvp_battery2s.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "common.h"
-#include "util.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/*
-	 * Getac Battery (Getac SMP-HHP-408) Information
-	 * Fuel gauge: BQ40Z50-R3
-	 */
-	[BATTERY_GETAC_SMP_HHP_408] = {
-		.fuel_gauge = {
-			.manuf_name = "Getac",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max = 8800,        /* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,   /* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_GETAC_SMP_HHP_408;
-
diff --git a/baseboard/intelrvp/adlrvp_battery3s.c b/baseboard/intelrvp/adlrvp_battery3s.c
deleted file mode 100644
index 315d5c247e..0000000000
--- a/baseboard/intelrvp/adlrvp_battery3s.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "common.h"
-#include "util.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/*
-	 * Getac Battery (Getac SMP-HHP-408) Information
-	 * Fuel gauge: BQ40Z50-R3
-	 */
-	[BATTERY_GETAC_SMP_HHP_408] = {
-		.fuel_gauge = {
-			.manuf_name = "Getac",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max = 13050,        /* mV */
-			.voltage_normal = 11400,
-			.voltage_min = 9000,
-			.precharge_current = 256,   /* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_GETAC_SMP_HHP_408;
-
diff --git a/baseboard/intelrvp/adlrvp_ioex_gpio.inc b/baseboard/intelrvp/adlrvp_ioex_gpio.inc
deleted file mode 100644
index e5522b02b3..0000000000
--- a/baseboard/intelrvp/adlrvp_ioex_gpio.inc
+++ /dev/null
@@ -1,31 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-IOEX(USB_C0_BB_RETIMER_RST,	EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW)
-IOEX(USB_C0_BB_RETIMER_LS_EN,	EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW)
-IOEX(USB_C0_USB_MUX_CNTRL_1,	EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P04), GPIO_OUT_LOW)
-IOEX(USB_C0_USB_MUX_CNTRL_0,	EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P05), GPIO_OUT_LOW)
-
-IOEX(USB_C1_BB_RETIMER_RST,	EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW)
-IOEX(USB_C1_BB_RETIMER_LS_EN,	EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW)
-IOEX(USB_C0_C1_OC,		EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P10), GPIO_OUT_HIGH)
-
-#if defined(HAS_TASK_PD_C2)
-IOEX(USB_C2_BB_RETIMER_RST,	EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW)
-IOEX(USB_C2_BB_RETIMER_LS_EN,	EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW)
-IOEX(USB_C2_USB_MUX_CNTRL_1,	EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P04), GPIO_OUT_LOW)
-IOEX(USB_C2_USB_MUX_CNTRL_0,	EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P05), GPIO_OUT_LOW)
-
-IOEX(USB_C3_BB_RETIMER_RST,	EXPIN(IOEX_C3_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW)
-IOEX(USB_C3_BB_RETIMER_LS_EN,	EXPIN(IOEX_C3_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW)
-IOEX(USB_C2_C3_OC,		EXPIN(IOEX_C3_PCA9675, 0, PCA9675_IO_P10), GPIO_OUT_HIGH)
-#endif
-
-/* ADL-RVP has custom GPIO implementation for reading board ID */
-UNIMPLEMENTED(BOARD_VERSION1)
-UNIMPLEMENTED(BOARD_VERSION2)
-UNIMPLEMENTED(BOARD_VERSION3)
diff --git a/baseboard/intelrvp/baseboard.c b/baseboard/intelrvp/baseboard.c
deleted file mode 100644
index 1e7b778c12..0000000000
--- a/baseboard/intelrvp/baseboard.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel-RVP family-specific configuration */
-
-#include "adc_chip.h"
-#include "charge_state.h"
-#include "espi.h"
-#include "fan.h"
-#include "hooks.h"
-#include "pca9555.h"
-#include "peci.h"
-#include "power.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "timer.h"
-
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-#ifdef CONFIG_TEMP_SENSOR
-/* Temperature sensors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SNS_AMBIENT] = {
-		.name = "Ambient",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v0_22k6_47k_4050b,
-		.idx = ADC_TEMP_SNS_AMBIENT,
-	},
-	[TEMP_SNS_BATTERY] = {
-		.name = "Battery",
-		.type = TEMP_SENSOR_TYPE_BATTERY,
-		.read = charge_get_battery_temp,
-		.idx = 0,
-	},
-	[TEMP_SNS_DDR] = {
-		.name = "DDR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v0_22k6_47k_4050b,
-		.idx = ADC_TEMP_SNS_DDR,
-	},
-#ifdef CONFIG_PECI
-	[TEMP_SNS_PECI] = {
-		.name = "PECI",
-		.type = TEMP_SENSOR_TYPE_CPU,
-		.read = peci_temp_sensor_get_val,
-		.idx = 0,
-	},
-#endif /* CONFIG_PECI */
-	[TEMP_SNS_SKIN] = {
-		.name = "Skin",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v0_22k6_47k_4050b,
-		.idx = ADC_TEMP_SNS_SKIN,
-	},
-	[TEMP_SNS_VR] = {
-		.name = "VR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v0_22k6_47k_4050b,
-		.idx = ADC_TEMP_SNS_VR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(15),
-	.temp_fan_max = C_TO_K(50),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SNS_AMBIENT] = thermal_a,
-	[TEMP_SNS_BATTERY] = thermal_a,
-	[TEMP_SNS_DDR] = thermal_a,
-#ifdef CONFIG_PECI
-	[TEMP_SNS_PECI] = thermal_a,
-#endif
-	[TEMP_SNS_SKIN] = thermal_a,
-	[TEMP_SNS_VR] = thermal_a,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-#endif /* CONFIG_TEMP_SENSOR */
-
-#ifdef CONFIG_FANS
-/* Physical fan config */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,
-	.pgood_gpio = GPIO_ALL_SYS_PWRGD,
-	.enable_gpio = GPIO_FAN_POWER_EN,
-};
-
-/* Physical fan rpm config */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = BOARD_FAN_MIN_RPM,
-	.rpm_start = BOARD_FAN_MIN_RPM,
-	.rpm_max = BOARD_FAN_MAX_RPM,
-};
-
-/* FAN channels */
-const struct fan_t fans[] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-#endif /* CONFIG_FANS */
-
-static void board_init(void)
-{
-	/* Enable SOC SPI */
-	gpio_set_level(GPIO_EC_SPI_OE_N, 1);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_LAST);
-
-static void board_interrupts_init(void)
-{
-	/* DC Jack interrupt */
-	gpio_enable_interrupt(GPIO_DC_JACK_PRESENT);
-}
-DECLARE_HOOK(HOOK_INIT, board_interrupts_init, HOOK_PRIO_FIRST);
-
-int ioexpander_read_intelrvp_version(int *port0, int *port1)
-{
-	if (pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO,
-		I2C_ADDR_PCA9555_BOARD_ID_GPIO,
-		PCA9555_CMD_INPUT_PORT_0, port0))
-		return -1;
-
-	return pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO,
-		I2C_ADDR_PCA9555_BOARD_ID_GPIO,
-		PCA9555_CMD_INPUT_PORT_1, port1);
-}
-
-__override void intel_x86_sys_reset_delay(void)
-{
-	/*
-	 * From MAX6818 Data sheet, Range of 'Debounce Duaration' is
-	 * Minimum - 20 ms, Typical - 40 ms, Maximum - 80 ms.
-	 */
-	udelay(60 * MSEC);
-}
diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h
deleted file mode 100644
index de4cb671ac..0000000000
--- a/baseboard/intelrvp/baseboard.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP board-specific configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-#include "compiler.h"
-#include "stdbool.h"
-
-#ifdef VARIANT_INTELRVP_EC_IT8320
-	#include "ite_ec.h"
-#elif defined(VARIANT_INTELRVP_EC_MCHP)
-	#include "mchp_ec.h"
-#elif defined(VARIANT_INTELRVP_EC_NPCX)
-	#include "npcx_ec.h"
-#else
-	#error "Define EC chip variant"
-#endif
-
-/*
- * Allow dangerous commands.
- * TODO: Remove this config before production.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* EC console commands  */
-#define CONFIG_CMD_CHARGER_DUMP
-#define CONFIG_CMD_KEYBOARD
-#define CONFIG_CMD_USB_PD_CABLE
-#define CONFIG_CMD_USB_PD_PE
-
-/* Host commands  */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-#define CONFIG_HOSTCMD_PD_CONTROL
-
-/* Port80 display */
-#define CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_SMART
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_SENSE_RESISTOR 5
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_TRICKLE_CHARGING
-
-/*
- * Don't allow the system to boot to S0 when the battery is low and unable to
- * communicate on locked systems (which haven't PD negotiated)
- */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT	15000
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		15001
-
-/* Keyboard */
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-
-/* UART */
-#define CONFIG_LOW_POWER_IDLE
-
-/* USB-A config */
-
-/* BC1.2 config */
-#ifdef HAS_TASK_USB_CHG_P0
-	#define CONFIG_CHARGE_RAMP_HW
-#endif
-
-/* Enable USB-PD REV 3.0 */
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PID 0x8086
-
-/* USB PD config */
-#if defined(BOARD_TGLRVPU_ITE_TCPMV1) || defined(BOARD_TGLRVPY_ITE_TCPMV1)
-	#define CONFIG_USB_PD_TCPMV1
-	#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#else
-	#define CONFIG_USB_DRP_ACC_TRYSRC
-	#define CONFIG_USB_PD_DECODE_SOP
-	#define CONFIG_USB_PD_TCPMV2
-	#define CONFIG_USB_PD_TCPM_MUX
-#endif
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_POWER_DELIVERY
-
-/* USB MUX */
-#ifdef CONFIG_USB_MUX_VIRTUAL
-	#define CONFIG_HOSTCMD_LOCATE_CHIP
-#endif
-#define CONFIG_USBC_SS_MUX
-
-/* SoC / PCH */
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* EC */
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_WP_ALWAYS
-
-/* Tablet mode */
-#define CONFIG_TABLET_MODE
-#define CONFIG_GMR_TABLET_MODE
-
-/* Verified boot */
-#define CONFIG_CRC8
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_VBOOT_HASH
-
-/*
- * Enable 1 slot of secure temporary storage to support
- * suspend/resume with read/write memory training.
- */
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/* Temperature sensor */
-#ifdef CONFIG_TEMP_SENSOR
-	#define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B
-	#define CONFIG_TEMP_SENSOR_POWER_GPIO   GPIO_EN_PP3300_A
-	#define CONFIG_THERMISTOR
-	#define CONFIG_THROTTLE_AP
-#ifdef CONFIG_PECI
-	#define CONFIG_PECI_COMMON
-#endif /* CONFIG_PECI */
-#endif /* CONFIG_TEMP_SENSOR */
-
-/* I2C ports */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-/* EC exclude modules */
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "module_id.h"
-#include "registers.h"
-
-FORWARD_DECLARE_ENUM(tcpc_rp_value);
-
-/* PWM channels */
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-/* FAN channels */
-enum fan_channel {
-	FAN_CH_0,
-	FAN_CH_COUNT,
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_TEMP_SNS_AMBIENT,
-	ADC_TEMP_SNS_DDR,
-	ADC_TEMP_SNS_SKIN,
-	ADC_TEMP_SNS_VR,
-	ADC_CH_COUNT,
-};
-
-/* Temperature sensors */
-enum temp_sensor_id {
-	TEMP_SNS_AMBIENT,
-	TEMP_SNS_BATTERY,
-	TEMP_SNS_DDR,
-#ifdef CONFIG_PECI
-	TEMP_SNS_PECI,
-#endif
-	TEMP_SNS_SKIN,
-	TEMP_SNS_VR,
-	TEMP_SENSOR_COUNT,
-};
-
-/* TODO(b:132652892): Verify the below numbers. */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* Define typical operating power */
-#define PD_OPERATING_POWER_MW  15000
-#define PD_MAX_VOLTAGE_MV      20000
-#define PD_MAX_CURRENT_MA      ((PD_MAX_POWER_MW/PD_MAX_VOLTAGE_MV) * 1000)
-#define DC_JACK_MAX_VOLTAGE_MV 19000
-
-/* TCPC gpios */
-struct tcpc_gpio_t {
-	enum gpio_signal pin;
-	uint8_t pin_pol;
-};
-
-/* VCONN gpios */
-struct vconn_gpio_t {
-	enum gpio_signal cc1_pin;
-	enum gpio_signal cc2_pin;
-	uint8_t pin_pol;
-};
-
-struct tcpc_gpio_config_t {
-	/* VBUS interrput */
-	struct tcpc_gpio_t vbus;
-	/* Source enable */
-	struct tcpc_gpio_t src;
-	/* Sink enable */
-	struct tcpc_gpio_t snk;
-#if defined(CONFIG_USBC_VCONN) && defined(CHIP_FAMILY_IT83XX)
-	/* Enable VCONN */
-	struct vconn_gpio_t vconn;
-#endif
-	/* Enable source ILIM */
-	struct tcpc_gpio_t src_ilim;
-};
-extern const struct tcpc_gpio_config_t tcpc_gpios[];
-
-struct tcpc_aic_gpio_config_t {
-	/* TCPC interrupt */
-	enum gpio_signal tcpc_alert;
-	/* PPC interrupt */
-	enum gpio_signal ppc_alert;
-	/* PPC interrupt handler */
-	void (*ppc_intr_handler)(int port);
-};
-extern const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[];
-
-void board_charging_enable(int port, int enable);
-void board_vbus_enable(int port, int enable);
-void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp);
-int ioexpander_read_intelrvp_version(int *port0, int *port1);
-void board_dc_jack_interrupt(enum gpio_signal signal);
-void tcpc_alert_event(enum gpio_signal signal);
-bool is_typec_port(int port);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/intelrvp/bc12.c b/baseboard/intelrvp/bc12.c
deleted file mode 100644
index 9f212fba4e..0000000000
--- a/baseboard/intelrvp/bc12.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP BC1.2 specific configuration */
-
-#include "common.h"
-#include "max14637.h"
-
-/* BC1.2 chip Configuration */
-#ifdef CONFIG_BC12_DETECT_MAX14637
-const struct max14637_config_t max14637_config[] = {
-	[TYPE_C_PORT_0] = {
-		.chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON_ODL,
-		.chg_det_pin = GPIO_USB_C0_BC12_CHG_DET_L,
-		.flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW,
-	},
-#ifdef HAS_TASK_PD_C1
-	[TYPE_C_PORT_1] = {
-		.chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON_ODL,
-		.chg_det_pin = GPIO_USB_C1_BC12_CHG_DET_L,
-		.flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW,
-	},
-#endif /* HAS_TASK_PD_C1 */
-};
-BUILD_ASSERT(ARRAY_SIZE(max14637_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
-#endif /* CONFIG_BC12_DETECT_MAX14637 */
diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk
deleted file mode 100644
index 6abf8bbe0c..0000000000
--- a/baseboard/intelrvp/build.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-#Intel RVP common files
-baseboard-y=baseboard.o
-baseboard-$(CONFIG_LED_COMMON)+=led.o led_states.o
-
-ifneq ($(CONFIG_USB_POWER_DELIVERY),)
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=chg_usb_pd.o
-baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_0_9)+=chg_usb_pd_mecc_0_9.o
-baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_0_9)+=usb_pd_policy_mecc_0_9.o
-baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=chg_usb_pd_mecc_1_0.o
-baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=usb_pd_policy_mecc_1_0.o
-endif
-
-#EC specific files
-baseboard-$(VARIANT_INTELRVP_EC_IT8320)+=ite_ec.o
-baseboard-$(VARIANT_INTELRVP_EC_MCHP)+=mchp_ec.o
-baseboard-$(VARIANT_INTELRVP_EC_NPCX)+=npcx_ec.o
-
-#BC1.2 specific files
-baseboard-$(CONFIG_BC12_DETECT_MAX14637)+=bc12.o
-
-#Common board specific files
-ifneq ($(filter y,$(BOARD_ADLRVPP_ITE) $(BOARD_ADLRVPM_ITE) \
-		$(BOARD_ADLRVPP_MCHP1521) $(BOARD_ADLRVPP_NPCX) \
-		$(BOARD_ADLRVPP_MCHP1727)),)
-baseboard-y+=adlrvp.o
-ifneq ($(BOARD_ADLRVPM_ITE),)
-baseboard-$(CONFIG_BATTERY_SMART)+=adlrvp_battery2s.o
-else
-baseboard-$(CONFIG_BATTERY_SMART)+=adlrvp_battery3s.o
-endif
-endif
diff --git a/baseboard/intelrvp/chg_usb_pd.c b/baseboard/intelrvp/chg_usb_pd.c
deleted file mode 100644
index 9f64cdd4e7..0000000000
--- a/baseboard/intelrvp/chg_usb_pd.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common USB PD charge configuration */
-
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "hooks.h"
-#include "tcpm/tcpci.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-bool is_typec_port(int port)
-{
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	return !(port == DEDICATED_CHARGE_PORT || port == CHARGE_PORT_NONE);
-#else
-	return !(port == CHARGE_PORT_NONE);
-#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */
-}
-
-static inline int board_dc_jack_present(void)
-{
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	return gpio_get_level(GPIO_DC_JACK_PRESENT);
-#else
-	return 0;
-#endif
-}
-
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-static void board_dc_jack_handle(void)
-{
-	struct charge_port_info charge_dc_jack;
-
-	/* System is booted from DC Jack */
-	if (board_dc_jack_present()) {
-		charge_dc_jack.current = (PD_MAX_POWER_MW * 1000) /
-					DC_JACK_MAX_VOLTAGE_MV;
-		charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV;
-	} else {
-		charge_dc_jack.current = 0;
-		charge_dc_jack.voltage = USB_CHARGER_VOLTAGE_MV;
-	}
-
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				DEDICATED_CHARGE_PORT, &charge_dc_jack);
-}
-#endif
-
-void board_dc_jack_interrupt(enum gpio_signal signal)
-{
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	board_dc_jack_handle();
-#endif
-}
-
-static void board_charge_init(void)
-{
-	int port, supplier;
-	struct charge_port_info charge_init = {
-		.current = 0,
-		.voltage = USB_CHARGER_VOLTAGE_MV,
-	};
-
-	/* Initialize all charge suppliers to seed the charge manager */
-	for (port = 0; port < CHARGE_PORT_COUNT; port++) {
-		for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; supplier++)
-			charge_manager_update_charge(supplier, port,
-				&charge_init);
-	}
-
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	board_dc_jack_handle();
-#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */
-}
-DECLARE_HOOK(HOOK_INIT, board_charge_init, HOOK_PRIO_DEFAULT);
-
-int board_set_active_charge_port(int port)
-{
-	int i;
-	/* charge port is a realy physical port */
-	int is_real_port = (port >= 0 &&
-			port < CHARGE_PORT_COUNT);
-	/* check if we are source vbus on that port */
-	int source = board_vbus_source_enabled(port);
-
-	if (is_real_port && source) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	/*
-	 * Do not enable Type-C port if the DC Jack is present.
-	 * When the Type-C is active port, hardware circuit will
-	 * block DC jack from enabling +VADP_OUT.
-	 */
-	if (port != DEDICATED_CHARGE_PORT && board_dc_jack_present()) {
-		CPRINTS("DC Jack present, Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */
-
-	/* Make sure non-charging ports are disabled */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		board_charging_enable(i, 0);
-	}
-
-	/* Enable charging port */
-	if (is_typec_port(port))
-		board_charging_enable(port, 1);
-
-	CPRINTS("New chg p%d", port);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-				CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c b/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c
deleted file mode 100644
index fa9f1e147f..0000000000
--- a/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel-RVP family-specific configuration */
-
-#include "console.h"
-#include "hooks.h"
-#include "tcpm/tcpci.h"
-#include "system.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void)
-{
-	/* Add code if TCPC chips need a reset */
-}
-
-int board_vbus_source_enabled(int port)
-{
-	int src_en = 0;
-
-	/* Only Type-C ports can source VBUS */
-	if (is_typec_port(port)) {
-		src_en = gpio_get_level(tcpc_gpios[port].src.pin);
-
-		src_en = tcpc_gpios[port].src.pin_pol ? src_en : !src_en;
-	}
-
-	return src_en;
-}
-
-void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	int ilim_en;
-
-	/* Only Type-C ports can source VBUS */
-	if (is_typec_port(port)) {
-		/* Enable SRC ILIM if rp is MAX single source current */
-		ilim_en = (rp ==  TYPEC_RP_3A0 &&
-			board_vbus_source_enabled(port));
-
-		gpio_set_level(tcpc_gpios[port].src_ilim.pin,
-				tcpc_gpios[port].src_ilim.pin_pol ?
-				ilim_en : !ilim_en);
-	}
-}
-
-void board_charging_enable(int port, int enable)
-{
-	gpio_set_level(tcpc_gpios[port].snk.pin,
-		tcpc_gpios[port].snk.pin_pol ? enable : !enable);
-
-}
-
-void board_vbus_enable(int port, int enable)
-{
-	gpio_set_level(tcpc_gpios[port].src.pin,
-		tcpc_gpios[port].src.pin_pol ? enable : !enable);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	int vbus_intr;
-
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	if (port == DEDICATED_CHARGE_PORT)
-		return 1;
-#endif
-
-	vbus_intr = gpio_get_level(tcpc_gpios[port].vbus.pin);
-
-	return tcpc_gpios[port].vbus.pin_pol ? vbus_intr : !vbus_intr;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (tcpc_gpios[i].vbus.pin == signal) {
-			schedule_deferred_pd_interrupt(i);
-			break;
-		}
-	}
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int i;
-
-	/* Check which port has the ALERT line set */
-	for (i = 0; i < CHARGE_PORT_COUNT; i++) {
-		/* No alerts for embdeded TCPC */
-		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED)
-			continue;
-
-		/* Add TCPC alerts if present */
-	}
-
-	return status;
-}
-
-void board_tcpc_init(void)
-{
-	int i;
-
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable TCPCx interrupt */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		gpio_enable_interrupt(tcpc_gpios[i].vbus.pin);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c
deleted file mode 100644
index 0c091efead..0000000000
--- a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel-RVP family-specific configuration */
-
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "console.h"
-#include "driver/ppc/sn5s330.h"
-#include "hooks.h"
-#include "tcpm/tcpci.h"
-#include "system.h"
-#include "usbc_ppc.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void)
-{
-	/* Add code if TCPC chips need a reset */
-}
-
-static void baseboard_tcpc_init(void)
-{
-	int i;
-
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		/* Enable PPC interrupts. */
-		if (tcpc_aic_gpios[i].ppc_intr_handler)
-			gpio_enable_interrupt(tcpc_aic_gpios[i].ppc_alert);
-
-		/* Enable TCPC interrupts. */
-		if (tcpc_config[i].bus_type != EC_BUS_TYPE_EMBEDDED)
-			gpio_enable_interrupt(tcpc_aic_gpios[i].tcpc_alert);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		/* No alerts for embdeded TCPC */
-		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED)
-			continue;
-
-		if (signal == tcpc_aic_gpios[i].tcpc_alert) {
-			schedule_deferred_pd_interrupt(i);
-			break;
-		}
-	}
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int i;
-
-	/* Check which port has the ALERT line set */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		/* No alerts for embdeded TCPC */
-		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED)
-			continue;
-
-		if (!gpio_get_level(tcpc_aic_gpios[i].tcpc_alert))
-			status |= PD_STATUS_TCPC_ALERT_0 << i;
-	}
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (!tcpc_aic_gpios[port].ppc_intr_handler)
-		return 0;
-
-	return !gpio_get_level(tcpc_aic_gpios[port].ppc_alert);
-}
-
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (tcpc_aic_gpios[i].ppc_intr_handler &&
-			signal == tcpc_aic_gpios[i].ppc_alert) {
-			tcpc_aic_gpios[i].ppc_intr_handler(i);
-			break;
-		}
-	}
-}
-
-void board_charging_enable(int port, int enable)
-{
-	if (ppc_vbus_sink_enable(port, enable))
-		CPRINTS("C%d: sink path %s failed",
-				port, enable ? "en" : "dis");
-}
diff --git a/baseboard/intelrvp/ite_ec.c b/baseboard/intelrvp/ite_ec.c
deleted file mode 100644
index bafddc5f9e..0000000000
--- a/baseboard/intelrvp/ite_ec.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP ITE EC specific configuration */
-
-#include "adc_chip.h"
-#include "common.h"
-#include "it83xx_pd.h"
-#include "keyboard_scan.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "timer.h"
-#include "usb_pd_tcpm.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SNS_AMBIENT] = {
-		.name = "ADC_TEMP_SNS_AMBIENT",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_AMBIENT_CHANNEL,
-	},
-	[ADC_TEMP_SNS_DDR] = {
-		.name = "ADC_TEMP_SNS_DDR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_DDR_CHANNEL,
-	},
-	[ADC_TEMP_SNS_SKIN] = {
-		.name = "ADC_TEMP_SNS_SKIN",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_SKIN_CHANNEL,
-	},
-	[ADC_TEMP_SNS_VR] = {
-		.name = "ADC_TEMP_SNS_VR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_VR_CHANNEL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/*
- * PWM HW channelx binding tachometer channelx for fan control.
- * Four tachometer input pins but two tachometer modules only,
- * so always binding [TACH_CH_TACH0A | TACH_CH_TACH0B] and/or
- * [TACH_CH_TACH1A | TACH_CH_TACH1B]
- */
-const struct fan_tach_t fan_tach[] = {
-	[PWM_HW_CH_DCR0] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR1] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR2] = {
-		.ch_tach = TACH_CH_TACH1A,
-		.fan_p = 2,
-		.rpm_re = 1,
-		.s_duty = 1,
-	},
-	[PWM_HW_CH_DCR3] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR4] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR5] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR6] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR7] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(fan_tach) == PWM_HW_CH_TOTAL);
-
-/* PWM channels */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = PWM_HW_CH_DCR2,
-		.flags = PWM_CONFIG_HAS_RPM_MODE,
-		.freq_hz = 30000,
-		.pcfsr_sel = PWM_PRESCALER_C7,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-#if defined(CONFIG_USBC_VCONN) && defined(CONFIG_USB_PD_TCPM_ITE_ON_CHIP)
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-#ifndef CONFIG_USBC_PPC_VCONN
-	/*
-	 * Setting VCONN low by disabling the power switch before
-	 * enabling the VCONN on respective CC line
-	 */
-	gpio_set_level(tcpc_gpios[port].vconn.cc1_pin,
-			!tcpc_gpios[port].vconn.pin_pol);
-	gpio_set_level(tcpc_gpios[port].vconn.cc2_pin,
-			!tcpc_gpios[port].vconn.pin_pol);
-
-	if (enabled)
-		gpio_set_level((cc_pin != USBPD_CC_PIN_1) ?
-				tcpc_gpios[port].vconn.cc2_pin :
-				tcpc_gpios[port].vconn.cc1_pin,
-				tcpc_gpios[port].vconn.pin_pol);
-#endif
-}
-#endif
diff --git a/baseboard/intelrvp/ite_ec.h b/baseboard/intelrvp/ite_ec.h
deleted file mode 100644
index c773a48b21..0000000000
--- a/baseboard/intelrvp/ite_ec.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP ITE EC specific configuration */
-
-#ifndef __CROS_EC_ITE_EC_H
-#define __CROS_EC_ITE_EC_H
-
-/* Optional feature - used by ITE */
-#define CONFIG_IT83XX_FLASH_CLOCK_48MHZ
-#define CONFIG_IT83XX_VCC_1P8V
-
-/* ADC channels */
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH13
-#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH15
-#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH6
-#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH1
-
-#ifdef CONFIG_USBC_VCONN
-	#define CONFIG_USBC_VCONN_SWAP
-	/* delay to turn on/off vconn */
-#endif
-#endif /* __CROS_EC_ITE_EC_H */
diff --git a/baseboard/intelrvp/led.c b/baseboard/intelrvp/led.c
deleted file mode 100644
index 47dad8994f..0000000000
--- a/baseboard/intelrvp/led.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Phaser
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_states.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-const int led_charge_lvl_1 = 5;
-
-const int led_charge_lvl_2 = 97;
-
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
-}
-
-void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/baseboard/intelrvp/led_states.c b/baseboard/intelrvp/led_states.c
deleted file mode 100644
index 5f8768bdd9..0000000000
--- a/baseboard/intelrvp/led_states.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED state control for octopus boards
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_states.h"
-
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-static enum led_states led_get_state(void)
-{
-	int  charge_lvl;
-	enum led_states new_state = LED_NUM_STATES;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Get percent charge */
-		charge_lvl = charge_get_percent();
-		/* Determine which charge state to use */
-		if (charge_lvl < led_charge_lvl_1)
-			new_state = STATE_CHARGING_LVL_1;
-		else if (charge_lvl < led_charge_lvl_2)
-			new_state = STATE_CHARGING_LVL_2;
-		else
-			new_state = STATE_CHARGING_FULL_CHARGE;
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			new_state = STATE_CHARGING_FULL_CHARGE;
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			new_state = STATE_DISCHARGE_S0;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			new_state = STATE_DISCHARGE_S3;
-		else
-			new_state = STATE_DISCHARGE_S5;
-		break;
-	case PWR_STATE_ERROR:
-		new_state = STATE_BATTERY_ERROR;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		new_state = STATE_CHARGING_FULL_CHARGE;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			new_state = STATE_FACTORY_TEST;
-		else
-			new_state = STATE_DISCHARGE_S0;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	return new_state;
-}
-
-static void led_update_battery(void)
-{
-	static uint8_t ticks, period;
-	static int led_state = LED_NUM_STATES;
-	int phase;
-	enum led_states desired_state = led_get_state();
-
-	/*
-	 * We always need to check the current state since the value could
-	 * have been manually overwritten. If we're in a new valid state,
-	 * update our ticks and period info. If our new state isn't defined,
-	 * continue using the previous one.
-	 */
-	if (desired_state != led_state && desired_state < LED_NUM_STATES) {
-		/* State is changing */
-		led_state = desired_state;
-		/* Reset ticks and period when state changes */
-		ticks = 0;
-
-		period = led_bat_state_table[led_state][LED_PHASE_0].time +
-			led_bat_state_table[led_state][LED_PHASE_1].time;
-
-	}
-
-	/* If this state is undefined, turn the LED off */
-	if (period == 0) {
-		CPRINTS("Undefined LED behavior for battery state %d,"
-			"turning off LED", led_state);
-		led_set_color_battery(LED_OFF);
-		return;
-	}
-
-	/*
-	 * Determine which phase of the state table to use. The phase is
-	 * determined if it falls within first phase time duration.
-	 */
-	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
-	ticks = (ticks + 1) % period;
-
-	/* Set the color for the given state and phase */
-	led_set_color_battery(led_bat_state_table[led_state][phase].color);
-}
-
-static enum pwr_led_states pwr_led_get_state(void)
-{
-	if (extpower_is_present()) {
-		if (charge_get_state() == PWR_STATE_CHARGE_NEAR_FULL)
-			return PWR_LED_STATE_OFF;
-		else
-			return PWR_LED_STATE_ON;
-	} else
-		return PWR_LED_STATE_SUSPEND_AC;
-}
-
-static void led_update_power(void)
-{
-	static uint8_t ticks, period;
-	static enum pwr_led_states led_state = PWR_LED_NUM_STATES;
-	int phase;
-	enum pwr_led_states desired_state = pwr_led_get_state();
-
-	/*
-	 * If we're in a new valid state, update our ticks and period info.
-	 * Otherwise, continue to use old state
-	 */
-	if (desired_state != led_state && desired_state < PWR_LED_NUM_STATES) {
-		/* State is changing */
-		led_state = desired_state;
-		/* Reset ticks and period when state changes */
-		ticks = 0;
-
-		period = led_pwr_state_table[led_state][LED_PHASE_0].time +
-			led_pwr_state_table[led_state][LED_PHASE_1].time;
-
-	}
-
-	/* If this state is undefined, turn the LED off */
-	if (period == 0) {
-		CPRINTS("Undefined LED behavior for power state %d,"
-			"turning off LED", led_state);
-		led_set_color_power(LED_OFF);
-		return;
-	}
-
-	/*
-	 * Determine which phase of the state table to use. The phase is
-	 * determined if it falls within first phase time duration.
-	 */
-	phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
-	ticks = (ticks + 1) % period;
-
-	/* Set the color for the given state and phase */
-	led_set_color_power(led_pwr_state_table[led_state][phase].color);
-}
-
-static void led_init(void)
-{
-	/* If battery LED is enabled, set it to "off" to start with */
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_color_battery(LED_OFF);
-}
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT);
-
-/* Called by hook task every hook tick (200 msec) */
-static void led_update(void)
-{
-	/*
-	 * If battery LED is enabled, set its state based on our power and
-	 * charge
-	 */
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_update_battery();
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_update_power();
-}
-DECLARE_HOOK(HOOK_TICK, led_update, HOOK_PRIO_DEFAULT);
diff --git a/baseboard/intelrvp/led_states.h b/baseboard/intelrvp/led_states.h
deleted file mode 100644
index 907ff5c8b8..0000000000
--- a/baseboard/intelrvp/led_states.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common functions for stateful LEDs (charger and power)
- */
-
-#ifndef __CROS_EC_BASEBOARD_LED_H
-#define __CROS_EC_BASEBOARD_LED_H
-
-#include "ec_commands.h"
-
-#define LED_INDEFINITE	UINT8_MAX
-#define LED_ONE_SEC	(1000 / HOOK_TICK_INTERVAL_MS)
-#define LED_OFF         EC_LED_COLOR_COUNT
-
-/*
- * All LED states should have one phase defined,
- * and an additional phase can be defined for blinking
- */
-enum led_phase {
-	LED_PHASE_0,
-	LED_PHASE_1,
-	LED_NUM_PHASES
-};
-
-/*
- * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1
- *
- * STATE_CHARGING_LVL_2 is when led_charge_level_1 <=
- * charge_percentage < led_charge_level_2
- *
- * STATE_CHARGING_FULL_CHARGE is when led_charge_level_2 <=
- * charge_percentage < 100
- */
-enum led_states {
-	STATE_CHARGING_LVL_1,
-	STATE_CHARGING_LVL_2,
-	STATE_CHARGING_FULL_CHARGE,
-	STATE_DISCHARGE_S0,
-	STATE_DISCHARGE_S0_BAT_LOW,
-	STATE_DISCHARGE_S3,
-	STATE_DISCHARGE_S5,
-	STATE_BATTERY_ERROR,
-	STATE_FACTORY_TEST,
-	LED_NUM_STATES
-};
-
-struct led_descriptor {
-	enum ec_led_colors color;
-	uint8_t time;
-};
-
-
-/* Charging LED state table - defined in board's led.c */
-extern struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES];
-
-/* Charging LED state level 1 - defined in board's led.c */
-extern const int led_charge_lvl_1;
-
-/* Charging LED state level 2 - defined in board's led.c */
-extern const int led_charge_lvl_2;
-
-enum pwr_led_states {
-	PWR_LED_STATE_ON,
-	PWR_LED_STATE_SUSPEND_AC,
-	PWR_LED_STATE_SUSPEND_NO_AC,
-	PWR_LED_STATE_OFF,
-	PWR_LED_NUM_STATES
-};
-
-/* Power LED state table - defined in board's led.c */
-extern const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES];
-
-/**
- * Set battery LED color - defined in board's led.c
- *
- * @param color		Color to set on battery LED
- *
- */
-void led_set_color_battery(enum ec_led_colors color);
-
-/**
- * Set power LED color - defined in board's led.c
- */
-void led_set_color_power(enum ec_led_colors color);
-
-#endif /* __CROS_EC_BASEBOARD_LED_H */
diff --git a/baseboard/intelrvp/mchp_ec.c b/baseboard/intelrvp/mchp_ec.c
deleted file mode 100644
index f1eb4678c1..0000000000
--- a/baseboard/intelrvp/mchp_ec.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP MCHP EC specific configuration */
-
-#include "adc_chip.h"
-#include "common.h"
-#include "keyboard_scan.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "timer.h"
-#include "usb_pd_tcpm.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80 us from 50 us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SNS_AMBIENT] = {
-		.name = "ADC_TEMP_SNS_AMBIENT",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_AMBIENT_CHANNEL,
-	},
-	[ADC_TEMP_SNS_DDR] = {
-		.name = "ADC_TEMP_SNS_DDR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_DDR_CHANNEL,
-	},
-	[ADC_TEMP_SNS_SKIN] = {
-		.name = "ADC_TEMP_SNS_SKIN",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_SKIN_CHANNEL,
-	},
-	[ADC_TEMP_SNS_VR] = {
-		.name = "ADC_TEMP_SNS_VR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_VR_CHANNEL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/*
- * TODO - Fan and tach table.
- * MCHP MEC1322 and MEC170x have fan speed controller(s)
- * whereas MEC152x only has multiple TACH and PWM modules.
- * MEC152x fan control will require a firmware layer that uses
- * specified TACH and PWM modules.
- */
-
-/* PWM channels */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-#ifdef CHIP_FAMILY_MEC172X
-		.channel = PWM_HW_CH_0,
-#else
-		.channel = PWM_HW_CH_4,
-#endif
-		.flags = PWM_CONFIG_HAS_RPM_MODE,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
diff --git a/baseboard/intelrvp/mchp_ec.h b/baseboard/intelrvp/mchp_ec.h
deleted file mode 100644
index 227ccaef6d..0000000000
--- a/baseboard/intelrvp/mchp_ec.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP MCHP EC specific configuration */
-
-#ifndef __CROS_EC_MCHP_EC_H
-#define __CROS_EC_MCHP_EC_H
-
-/* ADC channels */
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH7
-#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH4
-#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH3
-#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH1
-
-/*
- * ADC maximum voltage is a board level configuration.
- * MEC152x ADC can use an external 3.0 or 3.3V reference with
- * maximum values up to the reference voltage.
- * The ADC maximum voltage depends upon the external reference
- * voltage connected to MEC152x.
- */
-#define ADC_MAX_MVOLT 3000
-
-#endif /* __CROS_EC_MCHP_EC_H */
diff --git a/baseboard/intelrvp/npcx_ec.c b/baseboard/intelrvp/npcx_ec.c
deleted file mode 100644
index d6eca2e55b..0000000000
--- a/baseboard/intelrvp/npcx_ec.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP NPCX EC specific configuration */
-
-#include "adc_chip.h"
-#include "fan_chip.h"
-#include "keyboard_scan.h"
-#include "pwm_chip.h"
-#include "time.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SNS_AMBIENT] = {
-		.name = "ADC_TEMP_SNS_AMBIENT",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.input_ch = ADC_TEMP_SNS_AMBIENT_CHANNEL,
-	},
-	[ADC_TEMP_SNS_DDR] = {
-		.name = "ADC_TEMP_SNS_DDR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.input_ch = ADC_TEMP_SNS_DDR_CHANNEL,
-	},
-	[ADC_TEMP_SNS_SKIN] = {
-		.name = "ADC_TEMP_SNS_SKIN",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.input_ch = ADC_TEMP_SNS_SKIN_CHANNEL,
-	},
-	[ADC_TEMP_SNS_VR] = {
-		.name = "ADC_TEMP_SNS_VR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.input_ch = ADC_TEMP_SNS_VR_CHANNEL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = PWN_FAN_CHANNEL,
-		.flags = 0,
-		.freq = 30000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_2,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
diff --git a/baseboard/intelrvp/npcx_ec.h b/baseboard/intelrvp/npcx_ec.h
deleted file mode 100644
index 52bcb2dae6..0000000000
--- a/baseboard/intelrvp/npcx_ec.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP NPCX EC specific configuration */
-
-#ifndef __CROS_EC_NPCX_EC_H
-#define __CROS_EC_NPCX_EC_H
-
-#if !defined(__ASSEMBLER__)
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-#endif /* __ASSEMBLER__ */
-
-/* ADC channels */
-#define ADC_MAX_MVOLT			ADC_MAX_VOLT
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	NPCX_ADC_CH3
-#define ADC_TEMP_SNS_DDR_CHANNEL	NPCX_ADC_CH4
-#define ADC_TEMP_SNS_SKIN_CHANNEL	NPCX_ADC_CH2
-#define ADC_TEMP_SNS_VR_CHANNEL		NPCX_ADC_CH1
-
-/* KSO2 is inverted */
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-
-/* Fan */
-#define CONFIG_PWM
-#define PWN_FAN_CHANNEL		3
-
-/* GPIO64/65 are used as UART pins. */
-#define NPCX_UART_MODULE2	1
-
-#endif /* __CROS_EC_NPCX_EC_H */
diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c b/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c
deleted file mode 100644
index 6d173fd032..0000000000
--- a/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "console.h"
-#include "gpio.h"
-#include "system.h"
-#include "usb_mux.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	board_charging_enable(port, 0);
-
-	/* Provide VBUS */
-	board_vbus_enable(port, 1);
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	board_vbus_enable(port, 0);
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if PP5000 rail is enabled */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	board_set_vbus_source_current_limit(port, rp);
-}
diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c
deleted file mode 100644
index 29a538231f..0000000000
--- a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "console.h"
-#include "gpio.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = board_vbus_source_enabled(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if PP3300 rail is enabled */
-	return gpio_get_level(GPIO_EN_PP3300_A);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return ppc_is_vbus_present(port);
-}
-
-int board_vbus_source_enabled(int port)
-{
-	if (is_typec_port(port))
-		return ppc_is_sourcing_vbus(port);
-	return 0;
-}