diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-04-27 11:22:01 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-05-11 17:30:06 +0000 |
| commit | 200542008dca0aba2490e9993333be430b5fda6f (patch) | |
| tree | 0ae271ba489504f1e55582fcb36c92c8b226c286 /baseboard/intelrvp | |
| parent | 6f8dab1033786ac7071e48bc68add2b5ac271c82 (diff) | |
| download | chrome-ec-200542008dca0aba2490e9993333be430b5fda6f.tar.gz | |
treewide: Convert ESPI_DEFAULT_SCI_WIDTH_US to default VWIRE pulse width
In the corresponding bug, Intel has clarified that this SCI# pulse
length requirement is actually for all virtual wires, therefore this
patch renames CONFIG_ESPI_DEFAULT_SCI_WIDTH_US to
CONFIG_ESPI_DEFAULT_VW_WIDTH_US to reflect its broader purpose. All
pulses of virtual wire signals were converted to use this new pulse
width config option, and all GPIO pulses were converted back to their
original value (65 us).
BUG=b:227367177
BRANCH=brya
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1225b3e436cd1dca71c93500538a201d008781b3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3610694
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'baseboard/intelrvp')
| -rw-r--r-- | baseboard/intelrvp/adlrvp.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/baseboard/intelrvp/adlrvp.h b/baseboard/intelrvp/adlrvp.h index 000996e1d7..612cf58eba 100644 --- a/baseboard/intelrvp/adlrvp.h +++ b/baseboard/intelrvp/adlrvp.h @@ -33,9 +33,9 @@ /* Chipset */ #define CONFIG_CHIPSET_ALDERLAKE -/* ADL has new low-power features that require an extra-wide SCI pulse. */ -#undef CONFIG_ESPI_DEFAULT_SCI_WIDTH_US -#define CONFIG_ESPI_DEFAULT_SCI_WIDTH_US 150 +/* ADL has new low-power features that require extra-wide virtual wire pulses. */ +#undef CONFIG_ESPI_DEFAULT_VW_WIDTH_US +#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 150 /* USB PD config */ #if defined(HAS_TASK_PD_C3) |