diff options
author | Ayushee <ayushee.shah@intel.com> | 2020-07-15 09:16:06 -0700 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-08-27 00:40:30 +0000 |
commit | 865a57be356a76cebd8fd6429dcba9ed0a4cded7 (patch) | |
tree | 67bfd4dbb18f206e5c1add2eac1c8738efc307d2 /baseboard/intelrvp | |
parent | 82916b90e3f78f5cb48ee4f6cad536edbb329af4 (diff) | |
download | chrome-ec-865a57be356a76cebd8fd6429dcba9ed0a4cded7.tar.gz |
Intelrvp: Enable TCPMv2
This patch enables support for TCPMv2 for Intelrvp
BUG=b:142340399
BRANCH=none
TEST=TCPMv2/PD3.0 works properly on tglrvp.
Signed-off-by: Ayushee <ayushee.shah@intel.com>
Change-Id: If15fc23efbcd9716c322ad06bc78a8e16f957d8e
Signed-off-by: ravindr1 <ravindra@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2299841
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'baseboard/intelrvp')
-rw-r--r-- | baseboard/intelrvp/baseboard.h | 16 | ||||
-rw-r--r-- | baseboard/intelrvp/build.mk | 3 | ||||
-rw-r--r-- | baseboard/intelrvp/chg_usb_pd.c | 16 | ||||
-rw-r--r-- | baseboard/intelrvp/ite_ec.h | 1 | ||||
-rw-r--r-- | baseboard/intelrvp/vbus.c | 30 |
5 files changed, 24 insertions, 42 deletions
diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h index 49c2f7bdb9..5ee550a362 100644 --- a/baseboard/intelrvp/baseboard.h +++ b/baseboard/intelrvp/baseboard.h @@ -9,7 +9,7 @@ #define __CROS_EC_BASEBOARD_H #ifdef CHIP_FAMILY_IT83XX -#include "ite_ec.h" + #include "ite_ec.h" #endif /* CHIP_FAMILY_IT83XX */ /* @@ -81,6 +81,15 @@ #define CONFIG_USB_PID 0x8086 /* USB PD config */ +#if defined(BOARD_TGLRVPU_ITE_TCPMV1) || defined(BOARD_TGLRVPY_ITE_TCPMV1) + #define CONFIG_USB_PD_TCPMV1 +#else + #define CONFIG_USB_DRP_ACC_TRYSRC + #define CONFIG_USB_PD_DECODE_SOP + #define CONFIG_USB_PD_TCPMV2 + #define CONFIG_USB_PD_TCPM_MUX +#endif +#define CONFIG_USB_PD_DEBUG_LEVEL 1 #define CONFIG_USB_PD_ALT_MODE #define CONFIG_USB_PD_ALT_MODE_DFP #define CONFIG_USB_PD_DUAL_ROLE @@ -89,7 +98,6 @@ #define CONFIG_USB_PD_TRY_SRC #define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT #define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_TCPMV1 /* USB MUX */ #ifdef CONFIG_USB_MUX_VIRTUAL @@ -127,6 +135,7 @@ #define CONFIG_CRC8 #define CONFIG_SHA256_UNROLLED #define CONFIG_VBOOT_HASH + /* * Enable 1 slot of secure temporary storage to support * suspend/resume with read/write memory training. @@ -240,13 +249,12 @@ extern const struct tcpc_gpio_config_t tcpc_gpios[]; /* Reset PD MCU */ void board_reset_pd_mcu(void); -void vbus0_evt(enum gpio_signal signal); -void vbus1_evt(enum gpio_signal signal); void board_charging_enable(int port, int enable); void board_vbus_enable(int port, int enable); void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp); int ioexpander_read_intelrvp_version(int *port0, int *port1); void board_dc_jack_interrupt(enum gpio_signal signal); +void tcpc_alert_event(enum gpio_signal signal); #endif /* !__ASSEMBLER__ */ diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk index 12a62ffffc..d48d862fd5 100644 --- a/baseboard/intelrvp/build.mk +++ b/baseboard/intelrvp/build.mk @@ -24,6 +24,3 @@ baseboard-$(CONFIG_USB_MUX_ANX7440)+=usb_mux.o #USB Retimer specific files baseboard-$(CONFIG_USBC_RETIMER_INTEL_BB)+=retimer.o - -#VBUS detection specific files -baseboard-$(CONFIG_USB_PD_VBUS_DETECT_GPIO)+=vbus.o diff --git a/baseboard/intelrvp/chg_usb_pd.c b/baseboard/intelrvp/chg_usb_pd.c index c15ee886eb..8620268263 100644 --- a/baseboard/intelrvp/chg_usb_pd.c +++ b/baseboard/intelrvp/chg_usb_pd.c @@ -78,10 +78,18 @@ int pd_snk_is_vbus_provided(int port) void tcpc_alert_event(enum gpio_signal signal) { -#ifdef HAS_TASK_PDCMD - /* Exchange status with TCPCs */ - host_command_pd_send_status(PD_CHARGE_NO_CHANGE); -#endif + int port = -1; + int i; + + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (tcpc_gpios[i].vbus.pin == signal) { + port = i; + break; + } + } + + if (port != -1) + schedule_deferred_pd_interrupt(port); } void board_tcpc_init(void) diff --git a/baseboard/intelrvp/ite_ec.h b/baseboard/intelrvp/ite_ec.h index 9fc5def311..a09923dbb0 100644 --- a/baseboard/intelrvp/ite_ec.h +++ b/baseboard/intelrvp/ite_ec.h @@ -10,7 +10,6 @@ /* USB PD config */ #define CONFIG_USB_PD_TCPM_ITE_ON_CHIP -#define CONFIG_USB_PD_VBUS_DETECT_GPIO #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 /* Optional feature - used by ITE */ diff --git a/baseboard/intelrvp/vbus.c b/baseboard/intelrvp/vbus.c deleted file mode 100644 index 45ea3409cd..0000000000 --- a/baseboard/intelrvp/vbus.c +++ /dev/null @@ -1,30 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel BASEBOARD-RVP VBUS detection specific configuration */ - -#include "task.h" -#include "usb_charge.h" - -/* USB VBUS detection configuration */ -#ifdef CONFIG_USB_PD_VBUS_DETECT_GPIO -void vbus0_evt(enum gpio_signal signal) -{ -#ifdef HAS_TASK_USB_CHG_P0 - task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_VBUS, 0); -#endif - task_wake(TASK_ID_PD_C0); -} - -#ifdef HAS_TASK_PD_C1 -void vbus1_evt(enum gpio_signal signal) -{ -#ifdef HAS_TASK_USB_CHG_P1 - task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_VBUS, 0); -#endif - task_wake(TASK_ID_PD_C1); -} -#endif /* HAS_TASK_PD_C1 */ -#endif /* CONFIG_USB_PD_VBUS_DETECT_GPIO */ |