diff options
| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2019-05-30 16:25:15 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-06-13 23:02:44 +0000 |
| commit | 8ca44cb4eca69d44e9fce0b93b58be9c7d9d19f3 (patch) | |
| tree | 4913ea0403d24fc4574bfa2941ee4de7e28a000c /baseboard/intelrvp | |
| parent | 037eb91f65510d2949289f837c716b7fa997746f (diff) | |
| download | chrome-ec-8ca44cb4eca69d44e9fce0b93b58be9c7d9d19f3.tar.gz | |
intel_x86/power: Consolidate chipset specific power signals array
Currently chipset specific power signals are defined at board/baseboard
level. These power signals are moved to chipset specific file to minimize
the redundant power signals array defined for each board/baseboard.
BUG=b:134079574
BRANCH=none
TEST=make buildall -j
Change-Id: I351904f7cd2e0f27844c0711beb118d390219581
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'baseboard/intelrvp')
| -rw-r--r-- | baseboard/intelrvp/baseboard.c | 57 | ||||
| -rw-r--r-- | baseboard/intelrvp/baseboard.h | 20 |
2 files changed, 1 insertions, 76 deletions
diff --git a/baseboard/intelrvp/baseboard.c b/baseboard/intelrvp/baseboard.c index b48bda035f..af1edd2b9d 100644 --- a/baseboard/intelrvp/baseboard.c +++ b/baseboard/intelrvp/baseboard.c @@ -16,63 +16,6 @@ #include "temp_sensor.h" #include "thermistor.h" -/* GPIO for power signal */ -#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS -#define SLP_S3_SIGNAL_L VW_SLP_S3_L -#define SLP_S4_SIGNAL_L VW_SLP_S4_L -#else -#define SLP_S3_SIGNAL_L GPIO_PCH_SLP_S3_L -#define SLP_S4_SIGNAL_L GPIO_PCH_SLP_S4_L -#endif - -/* power signal list. Must match order of enum power_signal. */ -const struct power_signal_info power_signal_list[] = { - [X86_SLP_S0_DEASSERTED] = { - GPIO_PCH_SLP_S0_L, - POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT, - "SLP_S0_DEASSERTED", - }, - [X86_SLP_S3_DEASSERTED] = { - SLP_S3_SIGNAL_L, - POWER_SIGNAL_ACTIVE_HIGH, - "SLP_S3_DEASSERTED", - }, - [X86_SLP_S4_DEASSERTED] = { - SLP_S4_SIGNAL_L, - POWER_SIGNAL_ACTIVE_HIGH, - "SLP_S4_DEASSERTED", - }, - [X86_RSMRST_L_PGOOD] = { - GPIO_RSMRST_L_PGOOD, - POWER_SIGNAL_ACTIVE_HIGH, - "RSMRST_L_PGOOD", - }, - [X86_ALL_SYS_PWRGD] = { - GPIO_ALL_SYS_PWRGD, - POWER_SIGNAL_ACTIVE_HIGH, - "ALL_SYS_PWRGD", - }, -#if defined(CONFIG_CHIPSET_ICELAKE) - [X86_SLP_SUS_DEASSERTED] = { - GPIO_PCH_SLP_SUS_L, - POWER_SIGNAL_ACTIVE_HIGH, - "SLP_SUS_DEASSERTED", - }, - [X86_DSW_DPWROK] = { - GPIO_DSW_DPWROK, - POWER_SIGNAL_ACTIVE_HIGH, - "DSW_DPWROK", - }, -#elif defined(CONFIG_CHIPSET_COMETLAKE) - [PP5000_A_PGOOD] = { - GPIO_PP5000_A_PG_OD, - POWER_SIGNAL_ACTIVE_HIGH, - "PP5000_A_PGOOD", - }, -#endif -}; -BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); - /* Wake-up pins for hibernate */ const enum gpio_signal hibernate_wake_pins[] = { GPIO_AC_PRESENT, diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h index 5eaf4640de..b4bfbc7153 100644 --- a/baseboard/intelrvp/baseboard.h +++ b/baseboard/intelrvp/baseboard.h @@ -81,11 +81,11 @@ #define CONFIG_USBC_SS_MUX /* SoC / PCH */ +#define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_HOSTCMD_ESPI #define CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_HOST_EVENT -#define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 #define CONFIG_POWER_COMMON @@ -143,24 +143,6 @@ #include "registers.h" #include "usb_pd_tcpm.h" -enum power_signal { - X86_SLP_S0_DEASSERTED, - X86_SLP_S3_DEASSERTED, - X86_SLP_S4_DEASSERTED, - X86_RSMRST_L_PGOOD, - X86_ALL_SYS_PWRGD, -#if defined(CONFIG_CHIPSET_ICELAKE) - X86_SLP_SUS_DEASSERTED, - X86_DSW_DPWROK, -#elif defined(CONFIG_CHIPSET_COMETLAKE) - PP5000_A_PGOOD, -#else - #error "define Intel AP chipset variant" -#endif - /* Number of X86 signals */ - POWER_SIGNAL_COUNT -}; - /* PWM channels */ enum pwm_channel { PWM_CH_FAN, |