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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-04-21 10:50:45 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-04-21 22:22:13 +0000 |
| commit | e6f206838aff999d38292ffd907948c69844c7eb (patch) | |
| tree | a1fcd1b6bb73b2e2d380ba7c3c812927d4bd5103 /baseboard/intelrvp | |
| parent | 59cd12dfa8040c753d24d9d327db21d06d79ae71 (diff) | |
| download | chrome-ec-e6f206838aff999d38292ffd907948c69844c7eb.tar.gz | |
brask,brya,intelrvp: Increase SCI pulse width for Alder Lake chipsets
Alder Lake has new low-power features in the PMC and eSPI areas that
can require longer SCI pulse widths when these parts of the chipset are
in low power modes. The exact value is yet to be determined, but 150 us
has been determined empirically to avoid issues through testing scenarios
that easily demonstrated "lost" SCIs before the pulse width change.
BUG=b:227367177
BRANCH=brya
TEST=verified by Intel
Change-Id: I5436c3a15939cd034aac22344846447a5f5fb71d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3600138
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'baseboard/intelrvp')
| -rw-r--r-- | baseboard/intelrvp/adlrvp.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/baseboard/intelrvp/adlrvp.h b/baseboard/intelrvp/adlrvp.h index f1b7200d7e..000996e1d7 100644 --- a/baseboard/intelrvp/adlrvp.h +++ b/baseboard/intelrvp/adlrvp.h @@ -33,6 +33,10 @@ /* Chipset */ #define CONFIG_CHIPSET_ALDERLAKE +/* ADL has new low-power features that require an extra-wide SCI pulse. */ +#undef CONFIG_ESPI_DEFAULT_SCI_WIDTH_US +#define CONFIG_ESPI_DEFAULT_SCI_WIDTH_US 150 + /* USB PD config */ #if defined(HAS_TASK_PD_C3) #define CONFIG_USB_PD_PORT_MAX_COUNT 4 |