ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 205 deletions

diff --git a/baseboard/kukui/emmc_ite.c b/baseboard/kukui/emmc_ite.c
deleted file mode 100644
index 8c3e63064c..0000000000
--- a/baseboard/kukui/emmc_ite.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "endian.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "intc.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#include "bootblock_data.h"
-
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-enum emmc_cmd {
-	EMMC_ERROR = -1,
-	EMMC_IDLE = 0,
-	EMMC_PRE_IDLE,
-	EMMC_BOOT,
-};
-
-static void emmc_reset_spi_tx(void)
-{
-	/* Reset TX FIFO and count monitor */
-	IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR;
-	/* Send idle state (high/0xff) if master clocks in data. */
-	IT83XX_SPI_FCR = 0;
-}
-
-static void emmc_reset_spi_rx(void)
-{
-	/* End Rx FIFO access */
-	IT83XX_SPI_TXRXFAR = 0;
-	/* Reset RX FIFO and count monitor */
-	IT83XX_SPI_FCR = IT83XX_SPI_RXFR | IT83XX_SPI_RXFCMR;
-}
-
-/*
- * Set SPI module work as eMMC Alternative Boot Mode.
- * (CS# pin isn't required, and dropping data until CMD goes low)
- */
-static void emmc_enable_spi(void)
-{
-	/* Set SPI pin mux to eMMC (GPM2:CLK, GPM3:CMD, GPM6:DATA0) */
-	IT83XX_GCTRL_PIN_MUX0 |= BIT(7);
-	/* Enable eMMC Alternative Boot Mode */
-	IT83XX_SPI_EMMCBMR |= IT83XX_SPI_EMMCABM;
-	/* Reset TX and RX FIFO */
-	emmc_reset_spi_tx();
-	emmc_reset_spi_rx();
-	/* Response idle state (high) */
-	IT83XX_SPI_SPISRDR = 0xff;
-	/* FIFO will be overwritten once it's full */
-	IT83XX_SPI_GCR2 = 0;
-	/* Write to clear pending interrupt bits */
-	IT83XX_SPI_ISR = 0xff;
-	IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI;
-	/* Enable RX fifo full interrupt */
-	IT83XX_SPI_IMR = 0xff;
-	IT83XX_SPI_RX_VLISMR |= IT83XX_SPI_RVLIM;
-	IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_FIFO_FULL;
-	/*
-	 * Enable interrupt to detect AP's BOOTBLOCK_EN_L. So EC is able to
-	 * switch SPI module back to communication mode once BOOTBLOCK_EN_L
-	 * goes high (AP Jumped to bootloader).
-	 */
-	gpio_clear_pending_interrupt(GPIO_BOOTBLOCK_EN_L);
-	gpio_enable_interrupt(GPIO_BOOTBLOCK_EN_L);
-
-	disable_sleep(SLEEP_MASK_EMMC);
-	CPRINTS("eMMC emulation enabled");
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, emmc_enable_spi, HOOK_PRIO_FIRST);
-
-static void emmc_init_spi(void)
-{
-	/* Enable alternate function */
-	gpio_config_module(MODULE_SPI_FLASH, 1);
-}
-DECLARE_HOOK(HOOK_INIT, emmc_init_spi, HOOK_PRIO_INIT_SPI + 1);
-
-static void emmc_send_data_over_spi(uint8_t *tx, int tx_size, int rst_tx)
-{
-	int i;
-
-	/* Reset TX FIFO and count monitor */
-	if (rst_tx)
-		IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR;
-	/* CPU access TX FIFO1 and FIFO2 */
-	IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPUTFA;
-
-	/* Write response data to TX FIFO */
-	for (i = 0; i < tx_size; i += 4)
-		IT83XX_SPI_CPUWTFDB0 = *(uint32_t *)(tx + i);
-	/*
-	 * After writing data to TX FIFO is finished, this bit will
-	 * be to indicate the SPI slave controller.
-	 */
-	IT83XX_SPI_TXFCR = IT83XX_SPI_TXFS;
-	/* End CPU access TX FIFO */
-	IT83XX_SPI_TXRXFAR = 0;
-	/* SPI module access TX FIFO */
-	IT83XX_SPI_FCR = IT83XX_SPI_SPISRTXF;
-}
-
-static void emmc_bootblock_transfer(void)
-{
-	int tx_size, sent = 0, remaining = sizeof(bootblock_raw_data);
-	uint8_t *raw = (uint8_t *)bootblock_raw_data;
-	const uint32_t timeout_us = 200;
-	uint32_t start;
-
-	/*
-	 * HW will transmit the data of FIFO1 or FIFO2 in turn.
-	 * So when a FIFO is empty, we need to fill the FIFO out
-	 * immediately.
-	 */
-	emmc_send_data_over_spi(&raw[sent], 256, 1);
-	sent += 256;
-
-	while (sent < remaining) {
-		/* Wait for FIFO1 or FIFO2 have been transmitted */
-		start = __hw_clock_source_read();
-		while (!(IT83XX_SPI_TXFSR & BIT(0)) &&
-			(__hw_clock_source_read() - start < timeout_us))
-			;
-		/* Abort an ongoing transfer due to a command is received. */
-		if (IT83XX_SPI_ISR & IT83XX_SPI_RX_FIFO_FULL)
-			break;
-		/* fill out next 128 bytes to FIFO1 or FIFO2 */
-		tx_size = (remaining - sent) < 128 ? (remaining - sent) : 128;
-		emmc_send_data_over_spi(&raw[sent], tx_size, 0);
-		sent += tx_size;
-	}
-}
-
-static enum emmc_cmd emmc_parse_command(int index, uint32_t *cmd0)
-{
-	int32_t shift0;
-	uint32_t data[3];
-
-	data[0] = htobe32(cmd0[index]);
-	data[1] = htobe32(cmd0[index+1]);
-	data[2] = htobe32(cmd0[index+2]);
-
-	if ((data[0] & 0xff000000) != 0x40000000) {
-		/* Figure out alignment (cmd starts with 01) */
-		/* Number of leading ones. */
-		shift0 = __builtin_clz(~data[0]);
-
-		data[0] = (data[0] << shift0) | (data[1] >> (32-shift0));
-		data[1] = (data[1] << shift0) | (data[2] >> (32-shift0));
-	}
-
-	if (data[0] == 0x40000000 && data[1] == 0x0095ffff) {
-		/* 400000000095 GO_IDLE_STATE */
-		CPRINTS("goIdle");
-		return EMMC_IDLE;
-	}
-
-	if (data[0] == 0x40f0f0f0 && data[1] == 0xf0fdffff) {
-		/* 40f0f0f0f0fd GO_PRE_IDLE_STATE */
-		CPRINTS("goPreIdle");
-		return EMMC_PRE_IDLE;
-	}
-
-	if (data[0] == 0x40ffffff && data[1] == 0xfae5ffff) {
-		/* 40fffffffae5 BOOT_INITIATION */
-		CPRINTS("bootInit");
-		return EMMC_BOOT;
-	}
-
-	CPRINTS("eMMC error");
-	return EMMC_ERROR;
-}
-
-void spi_emmc_cmd0_isr(uint32_t *cmd0_payload)
-{
-	enum emmc_cmd cmd;
-
-	for (int i = 0; i < 8; i++) {
-		if (cmd0_payload[i] == 0xffffffff)
-			continue;
-
-		cmd = emmc_parse_command(i, &cmd0_payload[i]);
-
-		if (cmd == EMMC_IDLE || cmd == EMMC_PRE_IDLE) {
-			/* Abort an ongoing transfer. */
-			emmc_reset_spi_tx();
-			break;
-		}
-
-		if (cmd == EMMC_BOOT) {
-			emmc_bootblock_transfer();
-			break;
-		}
-	}
-}