adlprvp: add Alderlake RVP support

Following features are enabled and verified.
   1. Power sequencing
   2. Host communication
   3. USB TYPE-C - TCPC over PD AIC
   4. H1 Close Case Debug
   5. LED
   6. Keyboard

BRANCH=None
BUG=b:169551130
TEST=Build, flash and boot the Alderlake RVP platform to OS
make BOARD=adlrvpp_ite -j;
sudo util/flash_ec --board=adlrvpp_ite --image=<path>

Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Change-Id: I9d85e0cb93bc94f042f902b73ebd96a354d0f365
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435177
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>

5 files changed, 812 insertions, 0 deletions

diff --git a/board/adlrvpp_ite/board.c b/board/adlrvpp_ite/board.c
new file mode 100644
index 0000000000..875550a51e
--- /dev/null
+++ b/board/adlrvpp_ite/board.c
@@ -0,0 +1,423 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-P-RVP-ITE board-specific configuration */
+
+#include "bb_retimer.h"
+#include "button.h"
+#include "common.h"
+#include "charger.h"
+#include "fan.h"
+#include "fusb302.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "icelake.h"
+#include "isl9241.h"
+#include "it83xx_pd.h"
+#include "lid_switch.h"
+#include "pca9675.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "sn5s330.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "tablet_mode.h"
+#include "uart.h"
+#include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#include "gpio_list.h" /* Must come after other header files. */
+
+#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
+
+/*
+ * TCPC AIC used on all the ports are identical expect the I2C lines which
+ * are on the respective TCPC port's EC I2C line. Hence, I2C address and
+ * the GPIOs to control the retimers are also same for all the ports.
+ */
+#define TCPC_AIC_IOE_BB_RETIMER_RST	PCA9675_IO_P00
+#define TCPC_AIC_IOE_BB_RETIMER_LS_EN	PCA9675_IO_P01
+#define TCPC_AIC_IOE_USB_MUX_CNTRL_1	PCA9675_IO_P04
+#define TCPC_AIC_IOE_USB_MUX_CNTRL_0	PCA9675_IO_P05
+#define TCPC_AIC_IOE_OC			PCA9675_IO_P10
+
+#define TCPC_AIC_IOE_DIRECTION (PCA9675_DEFAULT_IO_DIRECTION & \
+	~(TCPC_AIC_IOE_BB_RETIMER_RST | TCPC_AIC_IOE_BB_RETIMER_LS_EN | \
+	TCPC_AIC_IOE_USB_MUX_CNTRL_1 | TCPC_AIC_IOE_USB_MUX_CNTRL_0 | \
+	TCPC_AIC_IOE_OC))
+
+/* Mutex for BB retimer shared NVM access */
+static struct mutex bb_nvm_mutex;
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	[I2C_CHAN_FLASH] = {
+		.name = "ec_flash",
+		.port = IT83XX_I2C_CH_A,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_PROG_SCL,
+		.sda = GPIO_EC_I2C_PROG_SDA,
+	},
+	[I2C_CHAN_BATT_CHG] = {
+		.name = "batt_chg",
+		.port = IT83XX_I2C_CH_B,
+		.kbps = 100,
+		.scl = GPIO_SMB_BS_CLK,
+		.sda = GPIO_SMB_BS_DATA,
+	},
+	[I2C_CHAN_TYPEC_0] = {
+		.name = "typec_0",
+		.port = IT83XX_I2C_CH_C,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P0,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P0,
+	},
+	[I2C_CHAN_TYPEC_1] = {
+		.name = "typec_1",
+		.port = IT83XX_I2C_CH_F,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P2,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P2,
+	},
+	[I2C_CHAN_TYPEC_2] = {
+		.name = "typec_2",
+		.port = IT83XX_I2C_CH_E,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P1,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P1,
+	},
+	[I2C_CHAN_TYPEC_3] = {
+		.name = "typec_3",
+		.port = IT83XX_I2C_CH_D,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P3,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P3,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* TCPC AIC GPIO Configuration */
+const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = {
+	[TYPE_C_PORT_0] = {
+		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P0,
+		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P0,
+	},
+	[TYPE_C_PORT_1] = {
+		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P1,
+		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P1,
+	},
+	[TYPE_C_PORT_2] = {
+		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P2,
+		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P2,
+	},
+	[TYPE_C_PORT_3] = {
+		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P3,
+		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P3,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* USB-C TCPC Configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[TYPE_C_PORT_0] = {
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it83xx_tcpm_drv,
+#ifdef CONFIG_INTEL_VIRTUAL_MUX
+		.usb23 = TYPE_C_PORT_0_USB2_NUM | (TYPE_C_PORT_0_USB3_NUM << 4),
+#endif
+	},
+	[TYPE_C_PORT_1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_1,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+#ifdef CONFIG_INTEL_VIRTUAL_MUX
+		.usb23 = TYPE_C_PORT_1_USB2_NUM | (TYPE_C_PORT_1_USB3_NUM << 4),
+#endif
+	},
+	[TYPE_C_PORT_2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_2,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+#ifdef CONFIG_INTEL_VIRTUAL_MUX
+		.usb23 = TYPE_C_PORT_2_USB2_NUM | (TYPE_C_PORT_2_USB3_NUM << 4),
+#endif
+	},
+	[TYPE_C_PORT_3] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_3,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+#ifdef CONFIG_INTEL_VIRTUAL_MUX
+		.usb23 = TYPE_C_PORT_3_USB2_NUM | (TYPE_C_PORT_3_USB3_NUM << 4),
+#endif
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* USB-C PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[TYPE_C_PORT_0] = {
+		.i2c_port = I2C_PORT_TYPEC_0,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
+		.drv = &sn5s330_drv,
+	},
+	[TYPE_C_PORT_1] = {
+		.i2c_port = I2C_PORT_TYPEC_1,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
+		.drv = &sn5s330_drv
+	},
+	[TYPE_C_PORT_2] = {
+		.i2c_port = I2C_PORT_TYPEC_2,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
+		.drv = &sn5s330_drv,
+	},
+	[TYPE_C_PORT_3] = {
+		.i2c_port = I2C_PORT_TYPEC_3,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
+		.drv = &sn5s330_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USB-C retimer Configuration */
+struct usb_mux usbc0_retimer = {
+	.usb_port = TYPE_C_PORT_0,
+	.driver = &bb_usb_retimer,
+	.i2c_port = I2C_PORT_TYPEC_0,
+	.i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR,
+};
+struct usb_mux usbc1_retimer = {
+	.usb_port = TYPE_C_PORT_1,
+	.driver = &bb_usb_retimer,
+	.i2c_port = I2C_PORT_TYPEC_1,
+	.i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR,
+};
+struct usb_mux usbc2_retimer = {
+	.usb_port = TYPE_C_PORT_2,
+	.driver = &bb_usb_retimer,
+	.i2c_port = I2C_PORT_TYPEC_2,
+	.i2c_addr_flags = I2C_PORT2_BB_RETIMER_ADDR,
+};
+struct usb_mux usbc3_retimer = {
+	.usb_port = TYPE_C_PORT_3,
+	.driver = &bb_usb_retimer,
+	.i2c_port = I2C_PORT_TYPEC_3,
+	.i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR,
+};
+
+/* USB muxes Configuration */
+const struct usb_mux usb_muxes[] = {
+	[TYPE_C_PORT_0] = {
+		.usb_port = TYPE_C_PORT_0,
+		.driver = &virtual_usb_mux_driver,
+		.hpd_update = &virtual_hpd_update,
+		.next_mux = &usbc0_retimer,
+	},
+	[TYPE_C_PORT_1] = {
+		.usb_port = TYPE_C_PORT_1,
+		.driver = &virtual_usb_mux_driver,
+		.hpd_update = &virtual_hpd_update,
+		.next_mux = &usbc1_retimer,
+	},
+	[TYPE_C_PORT_2] = {
+		.usb_port = TYPE_C_PORT_2,
+		.driver = &virtual_usb_mux_driver,
+		.hpd_update = &virtual_hpd_update,
+		.next_mux = &usbc2_retimer,
+	},
+	[TYPE_C_PORT_3] = {
+		.usb_port = TYPE_C_PORT_3,
+		.driver = &virtual_usb_mux_driver,
+		.hpd_update = &virtual_hpd_update,
+		.next_mux = &usbc3_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* Each TCPC have corresponding IO expander */
+const struct pca9675_ioexpander pca9675_iox[] = {
+	[TYPE_C_PORT_0] = {
+		.i2c_host_port = I2C_PORT_TYPEC_0,
+		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
+		.io_direction = TCPC_AIC_IOE_DIRECTION,
+	},
+	[TYPE_C_PORT_1] = {
+		.i2c_host_port = I2C_PORT_TYPEC_1,
+		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
+		.io_direction = TCPC_AIC_IOE_DIRECTION,
+	},
+	[TYPE_C_PORT_2] = {
+		.i2c_host_port = I2C_PORT_TYPEC_2,
+		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
+		.io_direction = TCPC_AIC_IOE_DIRECTION,
+	},
+	[TYPE_C_PORT_3] = {
+		.i2c_host_port = I2C_PORT_TYPEC_3,
+		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
+		.io_direction = TCPC_AIC_IOE_DIRECTION,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* Charger Chips */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Port 0 & 1 and 2 & 3 share same line for over current indication */
+	int ioex = port < TYPE_C_PORT_2 ?
+			TYPE_C_PORT_1 : TYPE_C_PORT_3;
+
+	if (is_overcurrented)
+		pca9675_update_pins(ioex, TCPC_AIC_IOE_OC, 0);
+	else
+		pca9675_update_pins(ioex, 0, TCPC_AIC_IOE_OC);
+}
+
+__override void bb_retimer_power_handle(const struct usb_mux *me, int on_off)
+{
+	/* Handle retimer's power domain.*/
+	if (on_off) {
+		/*
+		 * BB retimer NVM can be shared between multiple ports, hence
+		 * lock enabling the retimer until the current retimer request
+		 * is complete.
+		 */
+		mutex_lock(&bb_nvm_mutex);
+
+		pca9675_update_pins(me->usb_port,
+				TCPC_AIC_IOE_BB_RETIMER_LS_EN, 0);
+
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		msleep(1);
+		pca9675_update_pins(me->usb_port,
+				TCPC_AIC_IOE_BB_RETIMER_RST, 0);
+
+		/* Allow 20ms time for the retimer to be initialized. */
+		msleep(20);
+
+		mutex_unlock(&bb_nvm_mutex);
+	} else {
+		pca9675_update_pins(me->usb_port,
+				0, TCPC_AIC_IOE_BB_RETIMER_RST);
+		msleep(1);
+		pca9675_update_pins(me->usb_port,
+				0, TCPC_AIC_IOE_BB_RETIMER_LS_EN);
+	}
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	int ccd_intr_level = gpio_get_level(GPIO_CCD_MODE_ODL);
+
+	if (ccd_intr_level) {
+		/* Default set the SBU lines to AUX mode on TCPC-AIC */
+		pca9675_update_pins(TYPE_C_PORT_0, 0,
+			TCPC_AIC_IOE_USB_MUX_CNTRL_1 |
+			TCPC_AIC_IOE_USB_MUX_CNTRL_0);
+	} else {
+		/* Set the SBU lines to CCD mode on TCPC-AIC */
+		pca9675_update_pins(TYPE_C_PORT_0,
+			TCPC_AIC_IOE_USB_MUX_CNTRL_1,
+			TCPC_AIC_IOE_USB_MUX_CNTRL_0);
+	}
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+static void enable_h1_irq(void)
+{
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, enable_h1_irq, HOOK_PRIO_LAST);
+
+static void tcpc_aic_init(void)
+{
+	int i;
+
+	/* Initialize the IOEXPANDER on TCPC-AIC */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		pca9675_init(i);
+
+	/* Default set the SBU lines to AUX mode on both the TCPC-AIC */
+	board_connect_c0_sbu_deferred();
+
+	 /* Only TCPC-0 can do CCD or BSSB, Default set SBU lines to AUX */
+	pca9675_update_pins(TYPE_C_PORT_2, 0,
+		TCPC_AIC_IOE_USB_MUX_CNTRL_1 | TCPC_AIC_IOE_USB_MUX_CNTRL_0);
+}
+DECLARE_HOOK(HOOK_INIT, tcpc_aic_init, HOOK_PRIO_INIT_PCA9675);
+
+/******************************************************************************/
+/* PWROK signal configuration */
+/*
+ * On ADLRVP the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK
+ * signals are handled by the board. No EC control needed.
+ */
+const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {};
+const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {};
+const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+/*
+ * Returns board information (board id[7:0] and Fab id[15:8]) on success
+ * -1 on error.
+ */
+int board_get_version(void)
+{
+	int port0, port1;
+	int fab_id, board_id, bom_id;
+
+	if (ioexpander_read_intelrvp_version(&port0, &port1))
+		return -1;
+	/*
+	 * Port0: bit 0   - BOM ID(2)
+	 *        bit 2:1 - FAB ID(1:0) + 1
+	 * Port1: bit 7:6 - BOM ID(1:0)
+	 *        bit 5:0 - BOARD ID(5:0)
+	 */
+	bom_id = ((port1 & 0xC0) >> 6) | ((port0 & 0x01) << 2);
+	fab_id = ((port0 & 0x06) >> 1) + 1;
+	board_id = port1 & 0x3F;
+
+	CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id);
+
+	return board_id | (fab_id << 8);
+}
diff --git a/board/adlrvpp_ite/board.h b/board/adlrvpp_ite/board.h
new file mode 100644
index 0000000000..6d5cf6d246
--- /dev/null
+++ b/board/adlrvpp_ite/board.h
@@ -0,0 +1,165 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-P-RVP-ITE board-specific configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* ITE EC variant */
+#define VARIANT_INTELRVP_EC_IT8320
+
+#include "baseboard.h"
+
+/* MECC config */
+#define CONFIG_INTEL_RVP_MECC_VERSION_1_0
+
+/* Support early firmware selection */
+#define CONFIG_VBOOT_EFS2
+
+/* Chipset */
+#define CONFIG_CHIPSET_TIGERLAKE
+#define CONFIG_POWER_PP5000_CONTROL
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT			GPIO_BC_ACOK_EC
+#define GPIO_EC_INT_L			GPIO_EC_PCH_MKBP_INT_ODL_EC
+#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW_EC
+#define GPIO_LID_OPEN			GPIO_SMC_LID
+#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE_EC
+#define GPIO_PCH_WAKE_L			GPIO_PCH_WAKE_N
+#define GPIO_PCH_PWRBTN_L		GPIO_PM_PWRBTN_N_EC
+#define GPIO_PCH_RSMRST_L		GPIO_PM_RSMRST_EC
+#define GPIO_PCH_SLP_S0_L		GPIO_PCH_SLP_S0_N
+#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_R_L
+#define GPIO_PG_EC_DSW_PWROK		GPIO_VCCPDSW_3P3_EC
+#define GPIO_POWER_BUTTON_L		GPIO_MECH_PWR_BTN_ODL
+#define GPIO_RSMRST_L_PGOOD		GPIO_RSMRST_PWRGD_EC
+#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_EC
+#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL_EC
+#define GPIO_WP_L			GPIO_EC_WP_ODL
+#define GPIO_VOLUME_UP_L		GPIO_VOLUME_UP
+#define GPIO_VOLUME_DOWN_L		GPIO_VOL_DN_EC_R
+#define GPIO_DC_JACK_PRESENT		GPIO_STD_ADP_PRSNT
+#define GPIO_ESPI_RESET_L		GPIO_ESPI_RST_R
+#define GPIO_UART1_RX			GPIO_UART_SERVO_TX_EC_RX
+#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BAT_DET_EC
+#define GPIO_BAT_LED_RED_L		GPIO_LED_1_L_EC
+#define GPIO_PWR_LED_WHITE_L		GPIO_LED_2_L_EC
+#define GPIO_SLP_SUS_L			GPIO_PM_SLP_SUS_EC
+#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_PWRGD_EC
+#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD_EC
+#define GPIO_PCH_DSW_PWROK		GPIO_DSW_PWROK_EC
+#define GPIO_EN_PP3300_A		GPIO_EC_DS3
+#define GMR_TABLET_MODE_GPIO_L		GPIO_SLATE_MODE_INDICATION
+
+/* I2C ports & Configs */
+#define CONFIG_IT83XX_SMCLK2_ON_GPC7
+
+/* charger */
+#define CONFIG_CHARGER_ISL9241
+#define I2C_PORT_CHARGER	IT83XX_I2C_CH_B
+
+/* Battery */
+#define I2C_PORT_BATTERY	IT83XX_I2C_CH_B
+
+/* Board ID */
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO	IT83XX_I2C_CH_B
+#define I2C_ADDR_PCA9555_BOARD_ID_GPIO	0x22
+
+/* Port 80 */
+#define I2C_PORT_PORT80		IT83XX_I2C_CH_B
+#define PORT80_I2C_ADDR		MAX695X_I2C_ADDR1_FLAGS
+
+/* USB PD config */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 4
+#define CONFIG_INTEL_VIRTUAL_MUX
+#define CONFIG_USB_MUX_VIRTUAL
+#define PD_MAX_POWER_MW              60000
+
+/* USB-C I2C */
+#define I2C_PORT_TYPEC_0		IT83XX_I2C_CH_C
+#define I2C_PORT_TYPEC_1		IT83XX_I2C_CH_F
+#define I2C_PORT_TYPEC_2		IT83XX_I2C_CH_E
+#define I2C_PORT_TYPEC_3		IT83XX_I2C_CH_D
+
+/* TCPC AIC config */
+/* Support NXP PCA9675 I/O expander. */
+#define CONFIG_IO_EXPANDER_PCA9675
+#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX	0x21
+#define CONFIG_IO_EXPANDER_PORT_COUNT CONFIG_USB_PD_PORT_MAX_COUNT
+
+/* DC Jack charge ports */
+#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+#define DEDICATED_CHARGE_PORT CONFIG_USB_PD_PORT_MAX_COUNT
+
+/* PPC */
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define I2C_ADDR_SN5S330_TCPC_AIC_PPC	0x40
+
+/* TCPC */
+#define CONFIG_USB_PD_DISCHARGE
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+#define CONFIG_USB_PD_TCPM_FUSB302
+#define I2C_ADDR_FUSB302_TCPC_AIC	0x22
+
+/* Config BB retimer */
+#define CONFIG_USBC_RETIMER_INTEL_BB
+#define I2C_PORT0_BB_RETIMER_ADDR	0x50
+#define I2C_PORT1_BB_RETIMER_ADDR	0x51
+#define I2C_PORT2_BB_RETIMER_ADDR	0x52
+#define I2C_PORT3_BB_RETIMER_ADDR	0x53
+
+/* USB-C port's USB2 & USB3 port numbers */
+#ifdef CONFIG_INTEL_VIRTUAL_MUX
+	#define TYPE_C_PORT_0_USB2_NUM	1
+	#define TYPE_C_PORT_1_USB2_NUM	2
+	#define TYPE_C_PORT_2_USB2_NUM	3
+	#define TYPE_C_PORT_3_USB2_NUM	5
+
+	#define TYPE_C_PORT_0_USB3_NUM	(0+1)
+	#define TYPE_C_PORT_1_USB3_NUM	(1+1)
+	#define TYPE_C_PORT_2_USB3_NUM	(2+1)
+	#define TYPE_C_PORT_3_USB3_NUM	(3+1)
+#endif
+
+#ifndef __ASSEMBLER__
+
+enum adlrvp_i2c_channel {
+	I2C_CHAN_FLASH,
+	I2C_CHAN_BATT_CHG,
+	I2C_CHAN_TYPEC_0,
+	I2C_CHAN_TYPEC_1,
+	I2C_CHAN_TYPEC_2,
+	I2C_CHAN_TYPEC_3,
+	I2C_CHAN_COUNT,
+};
+
+enum adlrvp_charge_ports {
+	TYPE_C_PORT_0,
+	TYPE_C_PORT_1,
+	TYPE_C_PORT_2,
+	TYPE_C_PORT_3,
+};
+
+void espi_reset_pin_asserted_interrupt(enum gpio_signal signal);
+void extpower_interrupt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+void tcpc_alert_event(enum gpio_signal signal);
+void board_connect_c0_sbu(enum gpio_signal s);
+int board_get_version(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_ite/build.mk b/board/adlrvpp_ite/build.mk
new file mode 100644
index 0000000000..fe5f548324
--- /dev/null
+++ b/board/adlrvpp_ite/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Intel ADL-P-RVP-ITE board-specific configuration
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=intelrvp
+
+board-y=board.o
diff --git a/board/adlrvpp_ite/ec.tasklist b/board/adlrvpp_ite/ec.tasklist
new file mode 100644
index 0000000000..5cb10b2907
--- /dev/null
+++ b/board/adlrvpp_ite/ec.tasklist
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Intel ADL-P-RVP-ITE board-specific configuration.
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C2, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C3, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C2, pd_interrupt_handler_task, 2, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C3, pd_interrupt_handler_task, 3, ULTRA_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_ite/gpio.inc b/board/adlrvpp_ite/gpio.inc
new file mode 100644
index 0000000000..a35f475161
--- /dev/null
+++ b/board/adlrvpp_ite/gpio.inc
@@ -0,0 +1,183 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-P-RVP-ITE board-specific configuration */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Power sequencing interrupts */
+GPIO_INT(ALL_SYS_PWRGD_EC,	PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_EC,	PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PCH_SLP_S0_N,		PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCPDSW_3P3_EC,	PIN(I, 3), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCST_PWRGD,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PM_SLP_SUS_EC, 	PIN(K, 2), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_R_L,		PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+GPIO_INT(SLP_S4_R_L,		PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+
+/* Button interrupts */
+GPIO_INT(VOLUME_UP,		PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOL_DN_EC_R,		PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(SMC_LID,		PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
+GPIO_INT(MECH_PWR_BTN_ODL,	PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(EC_WP_ODL,		PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)
+
+/* DC Jack presence coming from +VADP_OUT */
+GPIO_INT(STD_ADP_PRSNT, 	PIN(J, 2), GPIO_INT_BOTH, board_dc_jack_interrupt) /* DC_JACK_PRESENT */
+
+GPIO_INT(BC_ACOK_EC,		PIN(K, 3), GPIO_INT_BOTH, extpower_interrupt) /* AC Present */
+
+GPIO_INT(UART_SERVO_TX_EC_RX,	PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt)
+
+/* USB-C interrupts */
+/* Using embedded TCPC for Port-0 */
+UNIMPLEMENTED(USBC_TCPC_ALRT_P0)
+GPIO(NC_USBC_TCPC_ALRT_P0,	PIN(I, 7), GPIO_INPUT)
+GPIO_INT(USBC_TCPC_ALRT_P1,	PIN(G, 0), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USBC_TCPC_ALRT_P2,	PIN(J, 1), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USBC_TCPC_ALRT_P3,	PIN(J, 3), GPIO_INT_BOTH, tcpc_alert_event)
+
+GPIO_INT(USBC_TCPC_PPC_ALRT_P1, PIN(C, 4), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P2, PIN(E, 5), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P3, PIN(E, 6), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(J, 5), GPIO_INT_BOTH, ppc_interrupt)
+
+#ifndef CONFIG_HOSTCMD_ESPI
+GPIO_INT(ESPI_RST_R,		PIN(D, 2), GPIO_INPUT)
+#endif
+
+#ifdef CONFIG_HOSTCMD_ESPI
+/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
+GPIO_INT(ESPI_RST_R,		PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
+#endif
+
+/* Sensor Interrupts */
+GPIO_INT(SLATE_MODE_INDICATION,	PIN(K, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, gmr_tablet_switch_isr)
+
+/* Power sequencing GPIOs */
+GPIO(SYS_RST_ODL_EC,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(PROCHOT_EC,		PIN(C, 0), GPIO_INPUT)
+GPIO(PM_RSMRST_EC,		PIN(C, 6), GPIO_OUT_LOW)
+GPIO(PM_PWRBTN_N_EC,		PIN(D, 0), GPIO_ODR_HIGH)
+GPIO(EC_SPI_OE_N,		PIN(I, 2), GPIO_OUT_LOW)
+
+GPIO(EC_PCH_MKBP_INT_ODL_EC,	PIN(B, 7), GPIO_ODR_HIGH)
+GPIO(EDP_BKLT_EN,		PIN(J, 6), GPIO_OUT_HIGH)
+GPIO(EC_DS3,			PIN(L, 4), GPIO_OUT_LOW)
+UNIMPLEMENTED(EN_PP5000)
+
+/*
+ * PCH_SYS_PWROK is an input, driven by the Silego chip. The common x86
+ * power sequencing expects that PCH_SYS_PWROK is an output and will drive
+ * this signal if GPIO_PCH_SYS_PWROK is configured. Map this pin as no-connect
+ * so that state can be monitored using the console.
+ */
+GPIO(PCH_PWROK_EC_R,	PIN(K, 4), GPIO_INPUT)
+GPIO(SYS_PWROK_EC,	PIN(D, 1), GPIO_INPUT)
+GPIO(DSW_PWROK_EC,	PIN(L, 6), GPIO_OUT_LOW)
+
+/* Host communication GPIOs */
+#ifndef CONFIG_HOSTCMD_ESPI
+GPIO(PLT_RST_L, 	PIN(H, 6), GPIO_INPUT | GPIO_PULL_UP) /* PCH_PLTRST_L */
+#endif
+GPIO(PCH_WAKE_N,	PIN(J, 0), GPIO_ODR_HIGH)
+
+/* Battery present */
+GPIO(BAT_DET_EC,	PIN(K, 0), GPIO_INPUT)
+
+/* LED */
+GPIO(LED_1_L_EC,	PIN(A, 6), GPIO_OUT_HIGH)	/* BAT_LED_GREEN_L LED_2_L */
+GPIO(LED_2_L_EC,	PIN(A, 7), GPIO_OUT_HIGH)	/* AC_LED_GREEN_L LED_1_L */
+
+/* H1 pins */
+GPIO(EC_H1_PACKET_MODE_EC,	PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW_EC,		PIN(K, 7), GPIO_OUT_LOW)
+
+/* Case Closed Debug Mode */
+GPIO_INT(CCD_MODE_ODL,	PIN(B, 5), GPIO_INT_BOTH, board_connect_c0_sbu)
+
+/* FAN control pins */
+GPIO(EC_THRM_SEN_PWRGATE_N,	PIN(K, 6), GPIO_OUT_LOW)
+
+/*
+ * I2C pins should be configure as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(EC_I2C_PROG_SCL,		PIN(B, 3), GPIO_INPUT)	/* I2C_A_SCL */
+GPIO(EC_I2C_PROG_SDA,		PIN(B, 4), GPIO_INPUT)	/* I2C_A_SDA */
+GPIO(SMB_BS_CLK,		PIN(C, 1), GPIO_INPUT)	/* I2C_B_SCL */
+GPIO(SMB_BS_DATA,		PIN(C, 2), GPIO_INPUT)	/* I2C_B_SDA */
+
+/* P0 IT83XX_I2C_CH_C */
+GPIO(USBC_TCPC_I2C_CLK_P0,	PIN(C, 7), GPIO_INPUT)	/* I2C_C_SCL */
+GPIO(USBC_TCPC_I2C_DATA_P0,	PIN(F, 7), GPIO_INPUT)	/* I2C_C_SDA */
+
+/* P1 IT83XX_I2C_CH_F */
+GPIO(USBC_TCPC_I2C_CLK_P2,	PIN(A, 4), GPIO_INPUT)	/* I2C_F_SCL */
+GPIO(USBC_TCPC_I2C_DATA_P2,	PIN(A, 5), GPIO_INPUT)	/* I2C_F_SDA */
+
+/* P2 IT83XX_I2C_CH_E */
+GPIO(USBC_TCPC_I2C_CLK_P1,	PIN(E, 0), GPIO_INPUT)	/* I2C_E_SCL */
+GPIO(USBC_TCPC_I2C_DATA_P1,	PIN(E, 7), GPIO_INPUT)	/* I2C_E_SDA */
+
+/* P3 IT83XX_I2C_CH_D */
+GPIO(USBC_TCPC_I2C_CLK_P3,	PIN(H, 1), GPIO_INPUT)	/* I2C_D_SCL */
+GPIO(USBC_TCPC_I2C_DATA_P3,	PIN(H, 2), GPIO_INPUT)	/* I2C_D_SDA */
+
+/* Unused 1.8V or 3.3V compatiable pins */
+GPIO(ESPI_CS1_N_R,		PIN(D, 3), GPIO_INPUT)
+GPIO(TP_GPIO_D4,		PIN(D, 4), GPIO_INPUT)
+GPIO(SUSWARN,			PIN(E, 1), GPIO_INPUT)
+GPIO(CPU_C10_GATE,		PIN(G, 1), GPIO_INPUT)
+GPIO(STD_ADPT_CNTRL_EC, 	PIN(G, 2), GPIO_INPUT)
+GPIO(BATT_DISABLE_EC,		PIN(H, 0), GPIO_INPUT)
+GPIO(ME_G3_TO_M3_EC,		PIN(H, 5), GPIO_INPUT)
+GPIO(SLP_S0_CS_EC,		PIN(I, 0), GPIO_INPUT)
+GPIO(TP_DEVELOPER_MODE_EC,	PIN(J, 4), GPIO_INPUT)
+GPIO(SMC_SHUTDOWN,		PIN(K, 5), GPIO_INPUT)
+GPIO(CPU_CAT_ERR_MECC,		PIN(L, 1), GPIO_INPUT)
+GPIO(SMC_ONOFF_N,		PIN(L, 3), GPIO_INPUT) /* Power button interrupt without H1 */
+GPIO(TP_GPIO_L5,		PIN(L, 5), GPIO_INPUT)
+GPIO(SMB_PCH_ALRT,		PIN(L, 7), GPIO_INPUT)
+GPIO(ESPI_ALERT0_R,		PIN(M, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Unused 3.3V compatiable pins */
+GPIO(TO_GPIO_A0,		PIN(A, 0), GPIO_INPUT)
+GPIO(TO_GPIO_A1,		PIN(A, 1), GPIO_INPUT)
+GPIO(TO_GPIO_A3,		PIN(A, 3), GPIO_INPUT)
+GPIO(TP_GPC3,			PIN(C, 3), GPIO_INPUT)
+GPIO(TP_GPC5,			PIN(C, 5), GPIO_INPUT)
+GPIO(TO_GPIO_E3,		PIN(E, 3), GPIO_INPUT)
+GPIO(TP_GPIO_H3,		PIN(H, 3), GPIO_INPUT)
+GPIO(TP_GPIO_H4,		PIN(H, 4), GPIO_INPUT)
+
+/* Alternate pins for I2C */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C F SCL/SDA A4/A5 */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C A SCL/SDA B3/B4 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C B SCL/SDA C1/C2 */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C E SCL/SDA E0/E7 */
+ALTERNATE(PIN_MASK(C, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)		/* I2C C SCL C7 */
+ALTERNATE(PIN_MASK(F, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)		/* I2C C SDA F7 */
+ALTERNATE(PIN_MASK(H, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C D SCL/SDA H1/H2 */
+
+/* Alternate pins for UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP) 	/* UART1 B0/B1 */
+
+/* Alternate pins for ADC */
+ALTERNATE(PIN_MASK(I, BIT(1) | BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 1,6 -> I1,I6 */
+ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 13,15 -> L0,L2 */
+
+/* Alternate pins for FAN */
+ALTERNATE(PIN_MASK(A, BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)		/* PWM2 A2 */
+ALTERNATE(PIN_MASK(D, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)		/* TACH1A D7 */