ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

6 files changed, 0 insertions, 580 deletions

diff --git a/board/adlrvpp_mchp1727/board.c b/board/adlrvpp_mchp1727/board.c
deleted file mode 100644
index 7e2b777e70..0000000000
--- a/board/adlrvpp_mchp1727/board.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-MCHP1727 board-specific configuration */
-#include "button.h"
-#include "fusb302.h"
-#include "lid_switch.h"
-#include "pca9675.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_pd_tcpm.h"
-#include "spi.h"
-#include "spi_chip.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	[I2C_CHAN_BATT_CHG] = {
-		.name = "batt_chg",
-		.port = I2C_PORT_CHARGER,
-		.kbps = 100,
-		.scl = GPIO_SMB_BS_CLK,
-		.sda = GPIO_SMB_BS_DATA,
-	},
-	[I2C_CHAN_TYPEC_0] = {
-		.name = "typec_0",
-		.port = I2C_PORT_TYPEC_0,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P0,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P0,
-	},
-	[I2C_CHAN_TYPEC_1] = {
-		.name = "typec_1",
-		.port = I2C_PORT_TYPEC_1,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P2,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P2,
-	},
-#if defined(HAS_TASK_PD_C2)
-	[I2C_CHAN_TYPEC_2] = {
-		.name = "typec_2",
-		.port = I2C_PORT_TYPEC_2,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P1,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P1,
-	},
-	[I2C_CHAN_TYPEC_3] = {
-		.name = "typec_3",
-		.port = I2C_PORT_TYPEC_3,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P3,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P3,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* USB-C TCPC Configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[TYPE_C_PORT_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_0,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#if defined(HAS_TASK_PD_C1)
-	[TYPE_C_PORT_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_1,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#endif
-#if defined(HAS_TASK_PD_C2)
-	[TYPE_C_PORT_2] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_2,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[TYPE_C_PORT_3] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_3,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
diff --git a/board/adlrvpp_mchp1727/board.h b/board/adlrvpp_mchp1727/board.h
deleted file mode 100644
index 50c666ece2..0000000000
--- a/board/adlrvpp_mchp1727/board.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-MCHP1727 board-specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* MCHP EC variant */
-#define VARIANT_INTELRVP_EC_MCHP
-
-/* UART for EC console */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 0
-
-#include "adlrvp.h"
-
-/*
- * External parallel crystal between XTAL1 and XTAL2 pins.
- *   #define CONFIG_CLOCK_SRC_EXTERNAL
- *   #define CONFIG_CLOCK_CRYSTAL
- * External single ended 32KHz 50% duty cycle input clock.
- *   #define CONFIG_CLOCK_SRC_EXTERNAL
- *   #undef CONFIG_CLOCK_CRYSTAL
- * Use internal silicon 32KHz oscillator
- *   #undef CONFIG_CLOCK_SRC_EXTERNAL
- *   CONFIG_CLOCK_CRYSTAL is a don't care
- */
-#undef	CONFIG_CLOCK_SRC_EXTERNAL
-
-/* MEC1727 integrated SPI chip 512KB SST25PF040C */
-#define CONFIG_SPI_FLASH_W25X40
-
-/*
- * Enable extra SPI flash and generic SPI
- * commands via EC UART
- */
-#define CONFIG_CMD_SPI_FLASH
-#define CONFIG_CMD_SPI_XFER
-
-/* MEC172x does not apply GP-SPI controllers */
-#undef CONFIG_MCHP_GPSPI
-
-/* ADC channels */
-#undef ADC_TEMP_SNS_AMBIENT_CHANNEL
-#undef ADC_TEMP_SNS_DDR_CHANNEL
-#undef ADC_TEMP_SNS_SKIN_CHANNEL
-#undef ADC_TEMP_SNS_VR_CHANNEL
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH3
-#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH5
-#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH4
-#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH0
-
-/*
- * ADC maximum voltage is a board level configuration.
- * MEC172x ADC can use an external 3.0 or 3.3V reference with
- * maximum values up to the reference voltage.
- * The ADC maximum voltage depends upon the external reference
- * voltage connected to MEC172x.
- */
-#undef ADC_MAX_MVOLT
-#define ADC_MAX_MVOLT 3300
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-/* Power sequencing */
-#define GPIO_EC_SPI_OE_N		GPIO_EC_SPI_OE_MECC
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
-#define GPIO_RSMRST_L_PGOOD		GPIO_RSMRST_PWRGD
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_PWRGD
-#define GPIO_PCH_SLP_S0_L		GPIO_PCH_SLP_S0_N
-#define GPIO_PG_EC_DSW_PWROK		GPIO_VCCPDSW_3P3
-#define GPIO_SLP_SUS_L			GPIO_PM_SLP_SUS_EC_N
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_PM_RSMRST_N
-#define GPIO_PCH_PWRBTN_L		GPIO_PM_PWRBTN_N
-#define GPIO_EN_PP3300_A		GPIO_EC_DS3
-#define GPIO_SYS_PWROK_EC		GPIO_SYS_PWROK
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_DSW_PWROK
-
-/* Sensors */
-#define GMR_TABLET_MODE_GPIO_L		GPIO_SLATE_MODE_INDICATION
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_EC_N
-
-/* Buttons */
-#define GPIO_LID_OPEN			GPIO_SMC_LID
-#define GPIO_VOLUME_UP_L		GPIO_VOLUME_UP
-#define GPIO_VOLUME_DOWN_L		GPIO_VOL_DN_EC
-#define GPIO_POWER_BUTTON_L		GPIO_MECH_PWR_BTN_ODL
-
-/* H1 */
-#define GPIO_WP_L			GPIO_EC_FLASH_WP_ODL
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-
-/* AC & Battery */
-#define GPIO_DC_JACK_PRESENT		GPIO_STD_ADP_PRSNT
-#define GPIO_AC_PRESENT			GPIO_BC_ACOK
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BAT_DET
-
-/* eSPI/Host communication */
-#define GPIO_ESPI_RESET_L		GPIO_LPC_ESPI_RST_N
-#define GPIO_PCH_WAKE_L			GPIO_SMC_WAKE_SCI_N_MECC
-#define GPIO_EC_INT_L			GPIO_EC_PCH_MKBP_INT_ODL
-
-/* LED */
-#define GPIO_BAT_LED_RED_L		GPIO_LED_1_L
-#define GPIO_PWR_LED_WHITE_L		GPIO_LED_2_L
-
-/* FAN */
-#define GPIO_FAN_POWER_EN		GPIO_THERM_SEN_MECC
-
-/* Charger */
-#define I2C_PORT_CHARGER	MCHP_I2C_PORT0
-
-/* Battery */
-#define I2C_PORT_BATTERY	MCHP_I2C_PORT0
-
-/* Board ID */
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	MCHP_I2C_PORT0
-
-/* Port 80 */
-#define I2C_PORT_PORT80		MCHP_I2C_PORT0
-
-/* USB-C I2C */
-#define I2C_PORT_TYPEC_0	MCHP_I2C_PORT6
-/*
- * Note: I2C for Type-C Port-1 is swapped with Type-C Port-2
- *       on the RVP to reduce BOM stuffing options.
- */
-#define I2C_PORT_TYPEC_1	MCHP_I2C_PORT3
-#if defined(HAS_TASK_PD_C2)
-#define I2C_PORT_TYPEC_2	MCHP_I2C_PORT7
-#define I2C_PORT_TYPEC_3	MCHP_I2C_PORT2
-#endif
-
-#ifndef __ASSEMBLER__
-
-enum adlrvp_i2c_channel {
-	I2C_CHAN_BATT_CHG,
-	I2C_CHAN_TYPEC_0,
-	I2C_CHAN_TYPEC_1,
-#if defined(HAS_TASK_PD_C2)
-	I2C_CHAN_TYPEC_2,
-	I2C_CHAN_TYPEC_3,
-#endif
-	I2C_CHAN_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_mchp1727/build.mk b/board/adlrvpp_mchp1727/build.mk
deleted file mode 100644
index 2a056943d4..0000000000
--- a/board/adlrvpp_mchp1727/build.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Intel ADL-P-RVP-MCHP1727 board-specific configuration
-#
-
-# the IC is Microchip MEC172x 416 KB total SRAM
-# MEC1723SZ variant is 144 pin, loads from external SPI flash
-# MEC1727SZ variant is 144 pin, loads from 512KB internal SPI flash
-# external SPI is 512KB
-# clock is Internal ROSC
-CHIP:=mchp
-CHIP_FAMILY:=mec172x
-CHIP_VARIANT:=mec1727sz
-CHIP_SPI_SIZE_KB:=512
-BASEBOARD:=intelrvp
-
-board-y=board.o
diff --git a/board/adlrvpp_mchp1727/ec.tasklist b/board/adlrvpp_mchp1727/ec.tasklist
deleted file mode 100644
index d640149caa..0000000000
--- a/board/adlrvpp_mchp1727/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Intel ADL-P-RVP-MCHP1727 board-specific configuration.
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_mchp1727/gpio.inc b/board/adlrvpp_mchp1727/gpio.inc
deleted file mode 100644
index 1eea86462c..0000000000
--- a/board/adlrvpp_mchp1727/gpio.inc
+++ /dev/null
@@ -1,262 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-MCHP1727 board-specific configuration */
-
-#include "baseboard/intelrvp/adlrvp_ioex_gpio.inc"
-/* include common gpio.inc under chip/mchp/lfw/... */
-#include "chip/mchp/lfw/gpio.inc"
-
-/* Power sequencing interrupts */
-GPIO_INT(ALL_SYS_PWRGD,		PIN(057), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD,		PIN(0221), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S0_N,		PIN(0243), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCPDSW_3P3,		PIN(0201), GPIO_INT_BOTH, power_signal_interrupt)
-/* TODO: GPIO_INT(VCCST_PWRGD_MECC,	PIN(0207), GPIO_INT_BOTH, power_signal_interrupt) */
-GPIO_INT(PM_SLP_SUS_EC_N, 	PIN(0227), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(PM_SLP_S3_N,		PIN(0161), GPIO_INT_BOTH, power_signal_interrupt)
-#else
-GPIO(PM_SLP_S3_N,		PIN(0161), GPIO_INPUT)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(PM_SLP_S4_N,		PIN(0162), GPIO_INT_BOTH, power_signal_interrupt)
-#else
-GPIO(PM_SLP_S4_N,		PIN(0162), GPIO_INPUT)
-#endif
-
-/* Button interrupts */
-GPIO_INT(VOLUME_UP,		PIN(036), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOL_DN_EC,		PIN(0254), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(SMC_LID,		PIN(0226), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-GPIO_INT(MECH_PWR_BTN_ODL,	PIN(0115), GPIO_INT_BOTH, power_button_interrupt)
-
-/* DC / AC interrupts, DC Jack presence coming from +VADP_OUT */
-GPIO_INT(STD_ADP_PRSNT, 	PIN(043), GPIO_INT_BOTH, board_dc_jack_interrupt) /* DC_JACK_PRESENT */
-GPIO_INT(BC_ACOK,		PIN(0156), GPIO_INT_BOTH, extpower_interrupt) /* AC Present */
-
-/* Sensor interrupt */
-GPIO_INT(SLATE_MODE_INDICATION,	PIN(0222), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* Flash WP interrupt */
-GPIO_INT(EC_FLASH_WP_ODL,	PIN(014), GPIO_INT_BOTH, switch_interrupt)
-
-/* Case Closed Debug Mode interrupt */
-GPIO_INT(CCD_MODE_ODL,		PIN(0175), GPIO_INT_BOTH, board_connect_c0_sbu)
-
-/* UART0 RX interrupt, RX input wake event */
-GPIO_INT(UART0_RX, PIN(0105), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, uart_deepsleep_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USBC_TCPC_ALRT_P0,	PIN(0143), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(0240), GPIO_INT_BOTH, ppc_interrupt)
-
-#if defined(HAS_TASK_PD_C1)
-GPIO_INT(USBC_TCPC_ALRT_P1,	PIN(0241), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P1, PIN(0101), GPIO_INT_BOTH, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_ALRT_P1,	PIN(0241), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P1,	PIN(0101), GPIO_INPUT)
-#endif
-
-#if defined(HAS_TASK_PD_C2)
-/* w/o rework: USBC_TCPC_ALRT_P2 -> VCI_OVRD_IN */
-GPIO_INT(USBC_TCPC_ALRT_P2,	PIN(0130), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P2, PIN(0144), GPIO_INT_BOTH, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_ALRT_P2,	PIN(0130), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P2,	PIN(0144), GPIO_INPUT)
-#endif
-
-#if defined(HAS_TASK_PD_C3)
-GPIO_INT(USBC_TCPC_ALRT_P3,	PIN(0242), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P3, PIN(0142), GPIO_INT_BOTH, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_ALRT_P3,	PIN(0242), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P3,	PIN(0142), GPIO_INPUT)
-#endif
-
-/* Host communication GPIOs */
-GPIO(SMC_WAKE_SCI_N_MECC,	PIN(051), GPIO_ODR_HIGH)
-GPIO(EC_PCH_MKBP_INT_ODL,	PIN(0127), GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO(LPC_ESPI_RST_N,		PIN(061), GPIO_INPUT)
-GPIO(PLT_RST_L, 		PIN(052), GPIO_INPUT) /* PCH_PLTRST_L */
-#endif
-
-/* Prochot GPIO */
-GPIO(PROCHOT_EC_N,		PIN(002), GPIO_INPUT)
-
-/* Power sequencing GPIOs */
-GPIO(SYS_RST_ODL,		PIN(060), GPIO_ODR_HIGH)
-GPIO(PM_RSMRST_N,		PIN(054), GPIO_OUT_LOW)
-GPIO(PM_PWRBTN_N,		PIN(016), GPIO_ODR_HIGH)
-/* w/o rework: EC_SPI_OE_MECC -> BGPO0 */
-GPIO(EC_SPI_OE_MECC,		PIN(042), GPIO_OUT_LOW)
-/* w/o rework: EC_DS3 -> VCI_OUT2 */
-GPIO(EC_DS3,			PIN(025), GPIO_OUT_LOW)
-UNIMPLEMENTED(EN_PP5000)
-
-/* PCH_PWROK_EC is an input, as it's driven by the Silego chip on RVP */
-GPIO(PCH_PWROK_EC,	PIN(0106), GPIO_INPUT)
-GPIO(SYS_PWROK,		PIN(0202), GPIO_OUT_LOW)
-GPIO(EC_DSW_PWROK,	PIN(034), GPIO_OUT_LOW)
-
-/* H1 GPIOs */
-GPIO(EC_H1_PACKET_MODE,		PIN(035), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW,		PIN(0102), GPIO_OUT_LOW)
-
-/* Battery present */
-GPIO(BAT_DET,		PIN(0206), GPIO_INPUT)
-
-/* EDP */
-GPIO(EDP_BKLT_EN_MECC,	PIN(022), GPIO_OUT_HIGH)
-
-/* LED */
-GPIO(LED_1_L,		PIN(0157), GPIO_OUT_HIGH)
-GPIO(LED_2_L,		PIN(0153), GPIO_OUT_HIGH)
-
-/* FAN control pins */
-GPIO(THERM_SEN_MECC,	PIN(0141), GPIO_OUT_LOW)
-
-/*
- * I2C pins should be configure as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(SMB_BS_CLK,		PIN(004), GPIO_INPUT)	/* I2C00_SCL */
-GPIO(SMB_BS_DATA,		PIN(003), GPIO_INPUT)	/* I2C00_SDA */
-GPIO(USBC_TCPC_I2C_CLK_P0,	PIN(0140), GPIO_INPUT)	/* I2C06_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P0,	PIN(0132), GPIO_INPUT)	/* I2C06_SDA */
-GPIO(USBC_TCPC_I2C_CLK_P1,	PIN(013), GPIO_INPUT)	/* I2C07_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P1,	PIN(012), GPIO_INPUT)	/* I2C07_SDA */
-GPIO(USBC_TCPC_I2C_CLK_P2,	PIN(010), GPIO_INPUT)	/* I2C03_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P2,	PIN(007), GPIO_INPUT)	/* I2C03_SDA */
-GPIO(USBC_TCPC_I2C_CLK_P3,	PIN(0155), GPIO_INPUT)	/* I2C02_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P3,	PIN(0154), GPIO_INPUT)	/* I2C02_SDA */
-
-/* Unused pins */
-GPIO(SML1_CLK_MECC,		PIN(0131), GPIO_INPUT)
-GPIO(CPU_CAT_ERR_MECC,		PIN(000), GPIO_INPUT)
-GPIO(ESPI_ALERT0_N,		PIN(063), GPIO_INPUT)
-GPIO(BATT_DISABLE_EC,		PIN(067), GPIO_INPUT)
-/* Unused: GPIO(SLP_S0_CS_N,		PIN(nVCI_IN0), GPIO_INPUT) */
-GPIO(CPU_C10_GATE_MECC,		PIN(023), GPIO_INPUT)
-GPIO(SMC_SDOWN_MECC,		PIN(0255), GPIO_INPUT)
-GPIO(STD_ADPT_CNTRL_GPIO,	PIN(0244), GPIO_INPUT)
-GPIO(SMC_ONOFF_N,		PIN(0114), GPIO_INPUT) /* Power button interrupt without H1 */
-GPIO(SUSWARN,			PIN(024), GPIO_INPUT)
-GPIO(ME_G3_TO_M3_EC,		PIN(033), GPIO_INPUT)
-
-/* Alternate pins for I2C */
-/* I2C pins alternate functions for ports 0, 2-3, 6-7
- * Configure I2C ports as I2C alternate function.
- * If board does not use external pull-ups then change GPIO flags
- * to enable internal pull-ups.
- * I2C00_SDA = GPIO_0003(Bank=0, bit=3) Func1
- * I2C00_SCL = GPIO_0004(Bank=0, bit=4) Func1
- * I2C02_SDA = GPIO_0154(Bank=3, bit=12) Func1
- * I2C02_SCL = GPIO_0155(Bank=3, bit=13) Func1
- * I2C03_SDA = GPIO_0007(Bank=0, bit=7) Func1
- * I2C03_SDL = GPIO_0010(Bank=0, bit=8) Func1
- * I2C06_SDA = GPIO_0132(Bank=2, bit=26) Func1
- * I2C06_SCL = GPIO_0140(Bank=3, bit=0) Func1
- * I2C07_SDA = GPIO_0012(Bank=0, bit=10) Func1
- * I2C07_SDL = GPIO_0013(Bank=0, bit=11) Func1
- */
-ALTERNATE(PIN_MASK(0,  0x00000D98), 1, MODULE_I2C, GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(2,  0x04000000), 1, MODULE_I2C, GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(3,  0x00003001), 1, MODULE_I2C, GPIO_ODR_HIGH)
-
-/* Alternate pins for ADC */
-/* VR_TMP/V_1P05 - GPIO44, SKIN_THERM_IN_EC - GPIO43, AMBIENT_TEMP - GPIO42, DDR_TEMP/EC_5V - GPIO41 */
-/* ADC pins
- * GPIO200/ADC00 = VR_TMP/V_1P05
- * GPIO203/ADC03 = AMBIENT_TEMP
- * GPIO204/ADC04 = SKIN_THERM_IN_EC
- * GPIO205/ADC05 = DDR_TEMP/EC_5V
- * ADC00 = GPIO_0200(Bank=4, bit=0) Func1
- * ADC03 = GPIO_0203(Bank=4, bit=3) Func1
- * ADC04 = GPIO_0204(Bank=4, bit=4) Func1
- * ADC05 = GPIO_0205(Bank=4, bit=5) Func1
- */
-ALTERNATE(PIN_MASK(4,  0x0039), 1, MODULE_ADC, GPIO_ANALOG)
-
-/*
- * Alternate pins for RPM-FAN control
- *
- * GPIO050/GTACH0 = CPU_TACHO_FAN
- * GPIO053/GPWM0 = CPU_PWM_FAN
- * GTACH0 = GPIO_050(Bank=1, bit=8) Func2
- * GPWM0 = GPIO_053(Bank=1, bit=11) Func3
- */
-ALTERNATE(PIN_MASK(1, 0x0100), 2, MODULE_PWM, GPIO_FLAG_NONE)
-ALTERNATE(PIN_MASK(1, 0x0800), 3, MODULE_PWM, GPIO_FLAG_NONE)
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2 (GPIO_OUT_LOW)
-/*
- * MEC172xH-SZ (144 pin package)
- * KSO00 = GPIO_0040 Func2 bank 1 bit 0
- * KSO01 = GPIO_0045 Func1 bank 1 bit 5
- * KSO02 = GPIO_0046 Func1 bank 1 bit 6
- * KSO03 = GPIO_0047 Func1 bank 1 bit 7
- * KSO04 = GPIO_0107 Func2 bank 2 bit 7
- * KSO05 = GPIO_0112 Func1 bank 2 bit 10
- * KSO06 = GPIO_0113 Func1 bank 2 bit 11
- * KSO07 = GPIO_0120 Func1 bank 2 bit 16
- * KSO08 = GPIO_0121 Func2 bank 2 bit 17
- * KSO09 = GPIO_0122 Func2 bank 2 bit 18
- * KSO10 = GPIO_0123 Func2 bank 2 bit 19
- * KSO11 = GPIO_0124 Func2 bank 2 bit 20
- * KSO12 = GPIO_0125 Func2 bank 2 bit 21
- * For 8x16 keyboard add KSO13 - KSO15
- * KSO13 = GPIO_0126 Func2 bank 2 bit 22
- * KSO14 = GPIO_0152 Func1 bank 3 bit 10
- * KSO15 = GPIO_0151 Func2 bank 3 bit 9
- *
- * KSI0 = GPIO_0017 Func1 bank 0 bit 15
- * KSI1 = GPIO_0020 Func1 bank 0 bit 16
- * KSI2 = GPIO_0021 Func1 bank 0 bit 17
- * KSI3 = GPIO_0026 Func1 bank 0 bit 22
- * KSI4 = GPIO_0027 Func1 bank 0 bit 23
- * KSI5 = GPIO_0030 Func1 bank 0 bit 24
- * KSI6 = GPIO_0031 Func1 bank 0 bit 25
- * KSI7 = GPIO_0032 Func1 bank 0 bit 26
- */
-/* KSO 0 Bank 1, Func2, bit 0 */
-ALTERNATE(PIN_MASK(1, 0x01), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-/* KSO 1-3 Bank 1, Func1, bits 5-7 */
-ALTERNATE(PIN_MASK(1, 0xA0), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-GPIO(KBD_KSO2, PIN(046), GPIO_KB_OUTPUT_COL2)
-#else
-/* KSO 1-3 Bank 1, Func1, bits 5-7 */
-ALTERNATE(PIN_MASK(1, 0xE0), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-#endif
-
-/* KSO 4, 8-12 Bank 2, Func2, bits 7, 17-21 */
-ALTERNATE(PIN_MASK(2, 0x003E0080), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-/* KSO 5-7, Bank 2, Func1, bits 10-11, 16 */
-ALTERNATE(PIN_MASK(2, 0x00010C00), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-
-/* KSI 0-7, Bank 0, Func1, bit 15-17, 22-26 */
-ALTERNATE(PIN_MASK(0, 0x07C38000), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-
-/*
- * ESPI_RESET# - GPIO_0061 Func 1, Bank 1 bit[17]
- * ESPI_ALERT# - GPIO_0063 Func 1, Bank 1 bit[19]
- * ESPI_CLK    - GPIO_0065 Func 1, Bank 1 bit[21]
- * ESPI_CS#    - GPIO_0066 Func 1, Bank 1 bit[22]
- * ESPI_IO0    - GPIO_0070 Func 1, Bank 1 bit[24]
- * ESPI_IO1    - GPIO_0071 Func 1, Bank 1 bit[25]
- * ESPI_IO2    - GPIO_0072 Func 1, Bank 1 bit[26]
- * ESPI_IO3    - GPIO_0073 Func 1, Bank 1 bit[27]
- */
-ALTERNATE(PIN_MASK(1, 0x0F6A0000), 1, MODULE_LPC, 0)
diff --git a/board/adlrvpp_mchp1727/vif_override.xml b/board/adlrvpp_mchp1727/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/adlrvpp_mchp1727/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->