diff options
| author | Karthikeyan Ramasubramanian <kramasub@chromium.org> | 2018-11-27 11:14:33 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-12-05 01:13:29 -0800 |
| commit | b91e34ca6bc7f3c5dae282eec5c2845ff5ec5b52 (patch) | |
| tree | 89cb1aa0d58eb67f6702f0ff5abc6b850116a0a1 /board/ampton/gpio.inc | |
| parent | 1caaa593b1abee713a6d5b30ac3c20a6713ddf76 (diff) | |
| download | chrome-ec-b91e34ca6bc7f3c5dae282eec5c2845ff5ec5b52.tar.gz | |
gpio: Add configuration for EC_PCH_RTCRST GPIO in octopus boards
This will help with using the hardware support to reset the RTC on the
SoC.
BUG=b:119678692
BRANCH=octopus
TEST=make -j buildall && Boot to ChromeOS. Create a forced scenario to
trigger an RTC reset and ensure that EC does not get reset while the SoC
boots to ChromeOS. Execute warm reboot from AP, cold reboot from EC and
wake from ec hibernate (10 iterations each) and suspend_stress_test for
50 iterations successfully.
Change-Id: Ib79012b43e397d4c27ca829b135115bebf77dedb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1354493
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'board/ampton/gpio.inc')
| -rw-r--r-- | board/ampton/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/ampton/gpio.inc b/board/ampton/gpio.inc index 2988ed44b0..e79acaccba 100644 --- a/board/ampton/gpio.inc +++ b/board/ampton/gpio.inc @@ -46,6 +46,7 @@ GPIO(LID_ACCEL_INT_L, PIN(J, 3), GPIO_INPUT | GPIO_SEL_1P8V) GPIO(PCH_PLTRST_L, PIN(E, 3), GPIO_INPUT) /* PLT_RST_L: Platform Reset from SoC */ GPIO(SYS_RESET_L, PIN(B, 6), GPIO_ODR_HIGH) /* SYS_RST_ODL */ +GPIO(PCH_RTCRST, PIN(K, 7), GPIO_OUT_LOW) /* EC_PCH_RTCRST */ GPIO(ENTERING_RW, PIN(C, 5), GPIO_OUT_LOW) /* EC_ENTERING_RW */ GPIO(PCH_WAKE_L, PIN(D, 1), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ @@ -58,7 +59,6 @@ GPIO(PP3300_PG, PIN(K, 1), GPIO_INPUT) /* PP3300_PG_OD */ GPIO(PMIC_EN, PIN(D, 7), GPIO_OUT_LOW) /* Enable A Rails via PMIC */ GPIO(PCH_RSMRST_L, PIN(C, 6), GPIO_OUT_LOW) /* RSMRST# to SOC. All _A rails now up. */ GPIO(PCH_SYS_PWROK, PIN(K, 4), GPIO_OUT_LOW) /* EC_PCH_PWROK. All S0 rails now up. */ -GPIO(PCH_RTCRST, PIN(K, 7), GPIO_OUT_LOW) /* EC_PCH_RTCRST */ /* Peripheral rails */ GPIO(ENABLE_BACKLIGHT, PIN(B, 5), GPIO_ODR_HIGH | |