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| author | Eric Yilun Lin <yllin@chromium.org> | 2020-05-12 11:46:37 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-05-15 07:39:55 +0000 |
| commit | 7e70fc5301b425ce8e0265b6e7ebb3cf9e7109bb (patch) | |
| tree | 35599948ab8bb041e00dac000cb96e649c8a4d4c /board/asurada/board.h | |
| parent | 55fc09f4be1c6a245c89e3be9816fb26d069f66c (diff) | |
| download | chrome-ec-release-R84-13099.B-master.tar.gz | |
asurada: enable PPC syv682x on C0/C1stabilize-quickfix-13099.93.B-masterstabilize-13099.94.B-masterstabilize-13099.90.B-masterstabilize-13099.85.B-masterstabilize-13099.73.B-masterstabilize-13099.70.B-masterstabilize-13099.118.B-masterstabilize-13099.110.B-masterstabilize-13099.101.B-masterrelease-R84-13099.B-master
Enable PPC on C0 and C1, where C1 port is optional and dependent
to the daughter board connected.
BUG=b:152562604
TEST=ensure C0/C1 can sink and source power.
BRANCH=master
Signed-off-by: Ting Shen <phoenixshen@google.com>
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Change-Id: I2fabe59562ffbe63e91b60f36b726d63fefdc83b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195721
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Diffstat (limited to 'board/asurada/board.h')
| -rw-r--r-- | board/asurada/board.h | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/board/asurada/board.h b/board/asurada/board.h index f97bbb2083..41433179e0 100644 --- a/board/asurada/board.h +++ b/board/asurada/board.h @@ -54,8 +54,16 @@ #define CONFIG_I2C_MASTER #define I2C_PORT_CHARGER IT83XX_I2C_CH_A #define I2C_PORT_BATTERY IT83XX_I2C_CH_A - -/* PD / USB-C */ +#define I2C_PORT_PPC0 IT83XX_I2C_CH_C +#define I2C_PORT_PPC1 IT83XX_I2C_CH_E + +/* PD / USB-C / PPC */ +#define CONFIG_CMD_PPC_DUMP +#define CONFIG_USBC_PPC +#define CONFIG_USBC_PPC_DEDICATED_INT +#define CONFIG_USBC_PPC_POLARITY +#define CONFIG_USBC_PPC_SYV682X +#define CONFIG_USBC_PPC_VCONN #define CONFIG_USBC_SS_MUX #define CONFIG_USBC_VCONN #define CONFIG_USBC_VCONN_SWAP @@ -63,15 +71,18 @@ #define CONFIG_USB_PD_ALT_MODE_DFP #define CONFIG_USB_PD_DEBUG_LEVEL 3 #define CONFIG_USB_PD_DECODE_SOP +#define CONFIG_USB_PD_DISCHARGE +#define CONFIG_USB_PD_DISCHARGE_PPC #define CONFIG_USB_PD_DUAL_ROLE #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 -#define CONFIG_USB_PD_LOGGING +#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0 #define CONFIG_USB_PD_PORT_MAX_COUNT 2 #define CONFIG_USB_PD_TCPMV1 #define CONFIG_USB_PD_TCPM_ITE_ON_CHIP #define CONFIG_USB_PD_TCPM_TCPCI #define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT /* TODO: */ +#define CONFIG_USB_PD_VBUS_DETECT_PPC +#define CONFIG_USB_PD_VBUS_MEASURE_CHARGER #define CONFIG_USB_PID 0x5566 /* TODO: update PID */ #define CONFIG_USB_POWER_DELIVERY |