diff options
| author | Teddy Shih <teddyshih@ami.corp-partner.google.com> | 2022-04-21 14:59:43 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-04-22 16:02:26 +0000 |
| commit | f16306464f53b936829cd0a93ebeaeab92817f94 (patch) | |
| tree | bb0d5564e160a86757619823dc7fae8c55371f61 /board/beadrix | |
| parent | 1b3d67a56e09f06cddc7d1b62975c5866d611e5c (diff) | |
| download | chrome-ec-f16306464f53b936829cd0a93ebeaeab92817f94.tar.gz | |
beadrix: Update EC gpio pin of EC_ENTERING_RW
To ensure EC notices H1 via EC_ENTERING_RW signal when EC is jumping
from RO to RW according to mainboard schematic, we add an EC gpio C7
pin of EC_ENTERING_RW2. Refer to Google Dio comment at (b:228938759)
"The workflow is:
1) When EC is jumping from RO to RW, it asserts EC_ENTERING_RW signal
to H1
2) Once H1 see the rising edge of EC_ENTERING_RW, it asserts
EC_IN_RW_OD high to notify AP"
and Google Ivan comment about CL of 2734058: Boten: Reroute
EC_ENTERING_RW to GPC7
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/
2734058
BRANCH=main
BUG=b:228938759
TEST=on beadrix, validate firmware_DevMode single manual test pass.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I39434860f54daf4ff8a8693effdcb9b061fe885a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3598693
Reviewed-by: Ivan Chen <yulunchen@google.com>
Commit-Queue: Ivan Chen <yulunchen@google.com>
Tested-by: Ivan Chen <yulunchen@google.com>
Diffstat (limited to 'board/beadrix')
| -rw-r--r-- | board/beadrix/board.c | 15 | ||||
| -rw-r--r-- | board/beadrix/gpio.inc | 1 |
2 files changed, 16 insertions, 0 deletions
diff --git a/board/beadrix/board.c b/board/beadrix/board.c index a22c2946e0..7e2e03629e 100644 --- a/board/beadrix/board.c +++ b/board/beadrix/board.c @@ -124,6 +124,21 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) pd_handle_cc_overvoltage(0); } +__override void board_pulse_entering_rw(void) +{ + /* + * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin + * which is active high by default. This causes Cr50 to think that the + * EC has jumped to its RW image even though this may not be the case. + * The pin is changed to GPIO_EC_ENTERING_RW2. + */ + gpio_set_level(GPIO_EC_ENTERING_RW, 1); + gpio_set_level(GPIO_EC_ENTERING_RW2, 1); + usleep(MSEC); + gpio_set_level(GPIO_EC_ENTERING_RW, 0); + gpio_set_level(GPIO_EC_ENTERING_RW2, 0); +} + /* Must come after other header files and interrupt handler declarations */ #include "gpio_list.h" diff --git a/board/beadrix/gpio.inc b/board/beadrix/gpio.inc index 6b90aba1c8..a7ca521e4b 100644 --- a/board/beadrix/gpio.inc +++ b/board/beadrix/gpio.inc @@ -95,6 +95,7 @@ GPIO(EC_SUB_IO_2_2, PIN(L, 2), GPIO_INPUT) /* Misc */ GPIO(EN_BL_OD, PIN(K, 4), GPIO_ODR_LOW) GPIO(EC_ENTERING_RW, PIN(G, 0), GPIO_OUT_LOW) +GPIO(EC_ENTERING_RW2, PIN(C, 7), GPIO_OUT_LOW) GPIO(CCD_MODE_ODL, PIN(H, 5), GPIO_ODR_HIGH) GPIO(EC_BATTERY_PRES_ODL, PIN(I, 4), GPIO_INPUT) GPIO(PEN_DET_ODL, PIN(J, 1), GPIO_INPUT | GPIO_PULL_UP) |