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authorGwendal Grignou <gwendal@chromium.org>2019-03-11 15:57:52 -0700
committerchrome-bot <chrome-bot@chromium.org>2019-03-26 04:42:55 -0700
commitbb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (patch)
treef6ada087f62246c3a9547e649ac8846b0ed6d5ab /board/coffeecake
parent0bfc511527cf2aebfa163c63a1d028419ca0b0c3 (diff)
downloadchrome-ec-bb266fc26fc05d4ab22de6ad7bce5b477c9f9140.tar.gz
common: replace 1 << digits, with BIT(digits)
Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'board/coffeecake')
-rw-r--r--board/coffeecake/board.c12
-rw-r--r--board/coffeecake/usb_pd_config.h6
2 files changed, 9 insertions, 9 deletions
diff --git a/board/coffeecake/board.c b/board/coffeecake/board.c
index bddfb0d159..e00c9e7b4b 100644
--- a/board/coffeecake/board.c
+++ b/board/coffeecake/board.c
@@ -140,15 +140,15 @@ void board_set_usb_output_voltage(int mv)
void board_config_pre_init(void)
{
/* Enable SYSCFG clock */
- STM32_RCC_APB2ENR |= 1 << 0;
+ STM32_RCC_APB2ENR |= BIT(0);
/* Enable DAC interface clock. */
- STM32_RCC_APB1ENR |= (1 << 29);
+ STM32_RCC_APB1ENR |= BIT(29);
/* Delay 1 APB clock cycle after the clock is enabled */
clock_wait_bus_cycles(BUS_APB, 1);
/* Set 5Vsafe Vdac */
board_set_usb_output_voltage(5000);
/* Remap USART DMA to match the USART driver */
- STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
+ STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
}
#ifdef CONFIG_SPI_FLASH
@@ -156,7 +156,7 @@ void board_config_pre_init(void)
static void board_init_spi2(void)
{
/* Remap SPI2 to DMA channels 6 and 7 */
- STM32_SYSCFG_CFGR1 |= (1 << 24);
+ STM32_SYSCFG_CFGR1 |= BIT(24);
/* Set pin NSS to general purpose output mode (01b). */
/* Set pins SCK, MISO, and MOSI to alternate function (10b). */
@@ -176,8 +176,8 @@ static void board_init_spi2(void)
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
/* Reset SPI2 */
- STM32_RCC_APB1RSTR |= (1 << 14);
- STM32_RCC_APB1RSTR &= ~(1 << 14);
+ STM32_RCC_APB1RSTR |= BIT(14);
+ STM32_RCC_APB1RSTR &= ~BIT(14);
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
diff --git a/board/coffeecake/usb_pd_config.h b/board/coffeecake/usb_pd_config.h
index 2282ea4e4b..e2c1dbb2db 100644
--- a/board/coffeecake/usb_pd_config.h
+++ b/board/coffeecake/usb_pd_config.h
@@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port)
#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
#define TIM_CCR_CS 1
-#define EXTI_COMP_MASK(p) (1 << 21)
+#define EXTI_COMP_MASK(p) BIT(21)
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
#define EXTI_XTSR STM32_EXTI_FTSR
@@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port)
static inline void pd_tx_spi_reset(int port)
{
/* Reset SPI1 */
- STM32_RCC_APB2RSTR |= (1 << 12);
- STM32_RCC_APB2RSTR &= ~(1 << 12);
+ STM32_RCC_APB2RSTR |= BIT(12);
+ STM32_RCC_APB2RSTR &= ~BIT(12);
}
/* Drive the CC line from the TX block */