ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 128 deletions

diff --git a/board/dingdong/usb_pd_config.h b/board/dingdong/usb_pd_config.h
deleted file mode 100644
index 2f01c275a8..0000000000
--- a/board/dingdong/usb_pd_config.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-/* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX_C0 17
-#define TIM_CLOCK_PD_RX_C0 1
-
-#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
-#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
-
-/* Timer channel */
-#define TIM_RX_CCR_C0 1
-#define TIM_TX_CCR_C0 1
-
-/* RX timer capture/compare register */
-#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
-#define TIM_RX_CCR_REG(p) TIM_CCR_C0
-
-/* TX and RX timer register */
-#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
-#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
-#define TIM_REG_TX(p) TIM_REG_TX_C0
-#define TIM_REG_RX(p) TIM_REG_RX_C0
-
-/* use the hardware accelerator for CRC */
-#define CONFIG_HW_CRC
-
-/* TX is using SPI1 on PB3-4 */
-#define SPI_REGS(p) STM32_SPI1_REGS
-
-static inline void spi_enable_clock(int port)
-{
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-}
-
-/* SPI1_TX no remap needed */
-#define DMAC_SPI_TX(p) STM32_DMAC_CH3
-
-/* RX is using COMP1 triggering TIM1 CH1 */
-#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
-#define CMP2OUTSEL 0
-
-#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
-#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) BIT(21)
-#define IRQ_COMP STM32_IRQ_COMP
-/* triggers packet detection on comparator falling edge */
-#define EXTI_XTSR STM32_EXTI_FTSR
-
-/* TIM1_CH1 no remap needed */
-#define DMAC_TIM_RX(p) STM32_DMAC_CH2
-
-/* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(int port)
-{
-	/* 40 Mhz pin speed on TX_EN (PA15) */
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xC0000000;
-	/* 40 MHz pin speed on SPI CLK/MOSI (PB3/4) TIM17_CH1 (PB9) */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C03C0;
-}
-
-/* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(int port)
-{
-	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= BIT(12);
-	STM32_RCC_APB2RSTR &= ~BIT(12);
-}
-
-/* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int port, int polarity)
-{
-	/* PB4 is SPI1_MISO */
-	gpio_set_alternate_function(GPIO_B, 0x0010, 0);
-
-	gpio_set_level(GPIO_PD_CC1_TX_EN, 1);
-}
-
-/* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int port, int polarity)
-{
-	/* output low on SPI TX (PB4) to disable the FET */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				   & ~(3 << (2*4)))
-				   |  (1 << (2*4));
-	/* put the low level reference in Hi-Z */
-	gpio_set_level(GPIO_PD_CC1_TX_EN, 0);
-}
-
-static inline void pd_select_polarity(int port, int polarity)
-{
-	/*
-	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
-	 * use VrefInt / 2 as INM (about 600mV)
-	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
-}
-
-/* Initialize pins used for TX and put them in Hi-Z */
-static inline void pd_tx_init(void)
-{
-	gpio_config_module(MODULE_USB_PD, 1);
-}
-
-static inline void pd_set_host_mode(int port, int enable) {}
-
-static inline void pd_config_init(int port, uint8_t power_role)
-{
-	/* Initialize TX pins and put them in Hi-Z */
-	pd_tx_init();
-}
-
-static inline int pd_adc_read(int port, int cc)
-{
-	/* only one CC line, assume other one is always low */
-	return (cc == 0) ? adc_read_channel(ADC_CH_CC1_PD) : 0;
-}
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */