Merge remote-tracking branch cros/main into firmware-keeby-14119.B-mainfirmware-keeby-14119.B-main

Relevant changes:

git log --oneline c5bd23a4b..b44d10f8f -- baseboard/dedede board/cappy2
board/corori board/driblee board/gooey board/haboki board/lalala
board/waddledoo2 common/charge_state_v2.c common/mkbp_* common/ocpc.c
common/usbc/usb_tc_drp_acc_trysrc_sm.c common/usbc/usb_sm.c
common/usbc/*_pd_* common/usbc/dp_alt_mode.c common/usbc/usb_prl_sm.c
common/usbc/usb_pe_drp_sm.c common/usb_charger.c common/usb_common.c
common/usbc_ocp.c driver/charger/sm5803.* driver/charger/isl923x.*
driver/tcpm/raa489000.* driver/tcpm/it83* include/power/icelake.h
include/intel_x86.h power/icelake.c power/intel_x86.c util/getversion.sh

42d03a001 config: change temp_sensor_power from config to gpio
e296efb28 usb_common: Fix CONFIG_USB_PD_DISCHARGE_TCPC typo
c346481f4 atomic: cast to unsigned when shifting
9b972a0f2 driver/tcpm/it83xx, it8xxx2: ITE inactive port return from HOOK
a499d8fd4 driver/tcpm/it83xx, it8xxx2: set sleep mask for mixed TCPC case
ed62e2583 TCPMv2: don't set the sleep mask for TCPC embedded in EC
c962696e8 motion_sensor: Remove |int_signal| field
86b216794 ocpc: modify pre-charge target condition
6f8336eb4 dedede: Set MKBP event wake mask to 0
02d034df0 dedede: add stylus fw_config
4f7cd7509 atomic: use atomic_t where it is possible
e3ffa0519 mkbp: change the type fifo_entries to atomic_t
bb4c47af0 usb: use atomic_t where possible
c6e513ee2 power/icelake: Add SLP_S5 as a watched power signal
d89e49b20 power: Introduce S4 as a real power state
ba8a3c9c0 chgstv2: Use chipset_in_state instead of naming states
23a975d12 i2c: Use declared initializers for i2c_ports: boards a-l
35865dbec TCPMv2: Guard DATA_RESET using CONFIG_USB_PD_DATA_RESET_MSG
d4d8243ed i2c: Use declared initializers for i2c_ports: baseboards
eba8d0305 RAA489000: Fixed RAA489000 max charging current
e78b83e0f TCPMv2: Delay Data Reset until mode entry request
6230e60fc TCPMv2: Support Data Reset as DFP, initiator
412246836 intel_x86: Apply chipset resume init and suspend complete hooks
f2809b72c config: rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI

BRANCH=None
BUG=b:202796060 b:207805856 b:167983049 b:208318528 b:181983966
BUG=b:207328258 b:195416058 b:205285137 b:199919093 b:207055975
BUG=b:129159505 b:204947672 b:141363146 b:207082842 b:205675485
TEST=`make -j buildall`

Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I980351977e11088a130e478df0701be4715f049b

18 files changed, 1647 insertions, 0 deletions

diff --git a/board/draco/battery.c b/board/draco/battery.c
new file mode 100644
index 0000000000..fbada9a9f1
--- /dev/null
+++ b/board/draco/battery.c
@@ -0,0 +1,107 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+/*
+ * Battery info for all Draco battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* DYNAPACK COSMAX Battery Information */
+	[BATTERY_DYNAPACK_COSMX] = {
+		/* RAJ240045 Fuel Gauge */
+		.fuel_gauge = {
+			.manuf_name = "333-2C-4C-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x43,
+				.reg_mask = 0x0003,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17600,
+			.voltage_normal		= 15400, /* mV */
+			.voltage_min		= 12000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= -10,
+			.discharging_max_c	= 60,
+		},
+	},
+	/* DYNAPACK HIGHPOWER Battery Information */
+	[BATTERY_DYNAPACK_HIGHPOWER] = {
+		/* RAJ240045 Fuel Gauge */
+		.fuel_gauge = {
+			.manuf_name = "333-2D-4C-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x43,
+				.reg_mask = 0x0003,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17600,
+			.voltage_normal		= 15400, /* mV */
+			.voltage_min		= 12000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= -10,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COSMX;
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+}
diff --git a/board/draco/board.c b/board/draco/board.c
new file mode 100644
index 0000000000..261aebf80c
--- /dev/null
+++ b/board/draco/board.c
@@ -0,0 +1,51 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "fw_config.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power_button.h"
+#include "power.h"
+#include "registers.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+#include "gpio_list.h" /* Must come after other header files. */
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+
+__override void board_cbi_init(void)
+{
+	config_usb_db_type();
+}
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
diff --git a/board/draco/board.h b/board/draco/board.h
new file mode 100644
index 0000000000..58abc1e694
--- /dev/null
+++ b/board/draco/board.h
@@ -0,0 +1,204 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Draco board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/*
+ * Early draco boards are not set up for vivaldi
+ */
+#undef CONFIG_KEYBOARD_VIVALDI
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+/* LED */
+#define CONFIG_LED_PWM
+#define CONFIG_LED_PWM_COUNT 2
+#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
+#undef CONFIG_LED_PWM_SOC_ON_COLOR
+#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
+#undef CONFIG_LED_PWM_LOW_BATT_COLOR
+#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_WHITE
+#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_WHITE
+#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_WHITE
+#define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER
+
+/* Sensors */
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_GMR_TABLET_MODE
+
+/* Buttons */
+#undef CONFIG_VOLUME_BUTTONS
+
+/* USB Type A Features */
+#define USB_PORT_COUNT			1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_USB_PD_TCPM_PS8815
+#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USBC_PPC_NX20P3483
+
+#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_VCONN_SWAP_DELAY		5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW	15000
+#define PD_MAX_POWER_MW		60000
+#define PD_MAX_CURRENT_MA	3000
+#define PD_MAX_VOLTAGE_MV	20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT			GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
+#define GPIO_WP_L			GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_C2_TCPC	NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_C2_PPC	NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_BC12	NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_MUX	NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS	0x50
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_SEQ_EC_DSW_PWROK
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#define CONFIG_FANS			FAN_CH_COUNT
+
+/* Charger defines */
+#define CONFIG_CHARGER_ISL9241
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_SENSE_RESISTOR		10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+
+/*
+ * Older boards have a different ADC assignment.
+ */
+
+#define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"	/* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_AMBIENT,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_TEMP_SENSOR_4_WWAN,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_AMBIENT,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_4_WWAN,
+	TEMP_SENSOR_COUNT
+};
+
+enum battery_type {
+	BATTERY_DYNAPACK_COSMX,
+	BATTERY_DYNAPACK_HIGHPOWER,
+	BATTERY_TYPE_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_LED2 = 0,		/* PWM0 (white charger) */
+	PWM_CH_LED3,			/* PWM1 (orange on DB) */
+	PWM_CH_LED1,			/* PWM2 (orange charger) */
+	PWM_CH_KBLIGHT,			/* PWM3 */
+	PWM_CH_FAN,			/* PWM5 */
+	PWM_CH_LED4,			/* PWM7 (white on DB) */
+	PWM_CH_COUNT
+};
+
+enum fan_channel {
+	FAN_CH_0 = 0,
+	FAN_CH_COUNT
+};
+
+enum mft_channel {
+	MFT_CH_0 = 0,
+	MFT_CH_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/draco/build.mk b/board/draco/build.mk
new file mode 100644
index 0000000000..61485378cd
--- /dev/null
+++ b/board/draco/build.mk
@@ -0,0 +1,25 @@
+# -*- makefile -*-
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Draco board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger_isl9241.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/draco/charger_isl9241.c b/board/draco/charger_isl9241.c
new file mode 100644
index 0000000000..85e0de90fe
--- /dev/null
+++ b/board/draco/charger_isl9241.c
@@ -0,0 +1,90 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+
+#include "charge_manager.h"
+#include "charge_state_v2.h"
+#include "charger.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "usbc_ppc.h"
+#include "usb_pd.h"
+#include "util.h"
+
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
+					  int max_ma, int charge_mv)
+{
+	charge_set_input_current_limit(MAX(charge_ma,
+					   CONFIG_CHARGER_INPUT_CURRENT),
+				       charge_mv);
+}
diff --git a/board/draco/ec.tasklist b/board/draco/ec.tasklist
new file mode 100644
index 0000000000..d866e2349e
--- /dev/null
+++ b/board/draco/ec.tasklist
@@ -0,0 +1,31 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C2, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/draco/fans.c b/board/draco/fans.c
new file mode 100644
index 0000000000..ca816af8ab
--- /dev/null
+++ b/board/draco/fans.c
@@ -0,0 +1,74 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan_chip.h"
+#include "fan.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2200,
+	.rpm_start = 2200,
+	.rpm_max = 4200,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+#ifndef CONFIG_FANS
+
+static void fan_slow(void)
+{
+	const int duty_pct = 33;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+static void fan_max(void)
+{
+	const int duty_pct = 100;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_FANS */
diff --git a/board/draco/fw_config.c b/board/draco/fw_config.c
new file mode 100644
index 0000000000..7dd00954e8
--- /dev/null
+++ b/board/draco/fw_config.c
@@ -0,0 +1,46 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+
+static union draco_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for draco if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union draco_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_PS8815,
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Draco FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+union draco_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
+{
+	return fw_config.usb_db;
+}
diff --git a/board/draco/fw_config.h b/board/draco/fw_config.h
new file mode 100644
index 0000000000..eea18a6e14
--- /dev/null
+++ b/board/draco/fw_config.h
@@ -0,0 +1,54 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_DRACO_FW_CONFIG_H_
+#define __BOARD_DRACO_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Draco board.
+ *
+ * Source of truth is the project/brya/draco/config.star configuration file.
+ */
+
+enum ec_cfg_usb_db_type {
+	DB_USB_ABSENT = 0,
+	DB_USB3_PS8815 = 1,
+	DB_USB_ABSENT2 = 15
+};
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+union draco_cbi_fw_config {
+	struct {
+		enum ec_cfg_usb_db_type			usb_db : 4;
+		uint32_t				sd_db : 2;
+		uint32_t				lte_db : 1;
+		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
+		uint32_t				audio : 3;
+		uint32_t				reserved_1 : 21;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union draco_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the USB daughter board type from FW_CONFIG.
+ *
+ * @return the USB daughter board type.
+ */
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
+
+#endif /* __BOARD_DRACO_FW_CONFIG_H_ */
diff --git a/board/draco/gpio.inc b/board/draco/gpio.inc
new file mode 100644
index 0000000000..715bff4f67
--- /dev/null
+++ b/board/draco/gpio.inc
@@ -0,0 +1,135 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C2_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C2_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C2_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C2_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_C2_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RST_ODL,                 PIN(9, 6), GPIO_ODR_LOW)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0)               /* GPIO60/PWM7 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0, GPIOC2/PWM1/I2C6_SCL0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+UNUSED(PIN(8, 1))       /* GPIO81 */
+UNUSED(PIN(D, 4))       /* GPIOD4 */
+UNUSED(PIN(5, 6))       /* GPIO56 */
+UNUSED(PIN(9, 3))       /* GPIO93 */
+UNUSED(PIN(9, 7))       /* GPIO97 */
+UNUSED(PIN(9, 5))       /* GPIO95 */
diff --git a/board/draco/i2c.c b/board/draco/i2c.c
new file mode 100644
index 0000000000..3db2e0c17b
--- /dev/null
+++ b/board/draco/i2c.c
@@ -0,0 +1,98 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "i2c.h"
+
+#define BOARD_ID_FAST_PLUS_CAPABLE	2
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,2",
+		.port = I2C_PORT_USB_C0_C2_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,2",
+		.port = I2C_PORT_USB_C0_C2_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,2",
+		.port = I2C_PORT_USB_C0_C2_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/*
+ * I2C controllers are initialized in main.c. This sets the speed much
+ * later, but before I2C peripherals are initialized.
+ */
+static void set_board_legacy_i2c_speeds(void)
+{
+	if (get_board_id() >= BOARD_ID_FAST_PLUS_CAPABLE)
+		return;
+
+	ccprints("setting USB DB I2C buses to 400 kHz\n");
+
+	i2c_set_freq(I2C_PORT_USB_C1_TCPC, I2C_FREQ_400KHZ);
+	i2c_set_freq(I2C_PORT_USB_C1_PPC, I2C_FREQ_400KHZ);
+}
+DECLARE_HOOK(HOOK_INIT, set_board_legacy_i2c_speeds, HOOK_PRIO_INIT_I2C - 1);
diff --git a/board/draco/keyboard.c b/board/draco/keyboard.c
new file mode 100644
index 0000000000..a9f033130d
--- /dev/null
+++ b/board/draco/keyboard.c
@@ -0,0 +1,25 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
diff --git a/board/draco/led.c b/board/draco/led.c
new file mode 100644
index 0000000000..74764a8ef4
--- /dev/null
+++ b/board/draco/led.c
@@ -0,0 +1,93 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Draco specific PWM LED settings: there are 2 LEDs on each side of the board,
+ * each one can be controlled separately. The LED colors are white or amber,
+ * and the default behavior is tied to the charging process: both sides are
+ * amber while charging the battery and white when the battery is charged.
+ */
+
+#include <stdint.h>
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "ec_commands.h"
+#include "led_pwm.h"
+#include "pwm.h"
+#include "util.h"
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_LEFT_LED,
+	EC_LED_ID_RIGHT_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+/*
+ * We only have a white and an amber LED, so setting any other color results in
+ * both LEDs being off. Cap at 50% to save power.
+ */
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+				/* Amber, White */
+	[EC_LED_COLOR_RED]    = {   0,   0 },
+	[EC_LED_COLOR_GREEN]  = {   0,   0 },
+	[EC_LED_COLOR_BLUE]   = {   0,   0 },
+	[EC_LED_COLOR_YELLOW] = {   0,   0 },
+	[EC_LED_COLOR_WHITE]  = {   0,  50 },
+	[EC_LED_COLOR_AMBER]  = {  50,   0 },
+};
+
+/* Two logical LEDs with amber and white channels. */
+struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
+	{
+		.ch0 = PWM_CH_LED1,
+		.ch1 = PWM_CH_LED2,
+		.ch2 = PWM_LED_NO_CHANNEL,
+		.enable = &pwm_enable,
+		.set_duty = &pwm_set_duty,
+	},
+	{
+		.ch0 = PWM_CH_LED3,
+		.ch1 = PWM_CH_LED4,
+		.ch2 = PWM_LED_NO_CHANNEL,
+		.enable = &pwm_enable,
+		.set_duty = &pwm_set_duty,
+	},
+};
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	memset(brightness_range, '\0',
+	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+	brightness_range[EC_LED_COLOR_WHITE] = 100;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	enum pwm_led_id pwm_id;
+
+	/* Convert ec_led_id to pwm_led_id. */
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		pwm_id = PWM_LED0;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		pwm_id = PWM_LED1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (brightness[EC_LED_COLOR_WHITE])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
+	else
+		/* Otherwise, the "color" is "off". */
+		set_pwm_led_color(pwm_id, -1);
+
+	return EC_SUCCESS;
+}
diff --git a/board/draco/pwm.c b/board/draco/pwm.c
new file mode 100644
index 0000000000..2203f14c8d
--- /dev/null
+++ b/board/draco/pwm.c
@@ -0,0 +1,71 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED2] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_LED3] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_LED1] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
+		.freq = 1000
+	},
+	[PWM_CH_LED4] = {
+		.channel = 7,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * Turn off all the LEDs.
+	 * Turn on the fan at 100%.
+	 */
+	pwm_enable(PWM_CH_LED1, 1);
+	pwm_set_duty(PWM_CH_LED1, 0);
+	pwm_enable(PWM_CH_LED2, 1);
+	pwm_set_duty(PWM_CH_LED2, 0);
+	pwm_enable(PWM_CH_LED3, 1);
+	pwm_set_duty(PWM_CH_LED3, 0);
+	pwm_enable(PWM_CH_LED4, 1);
+	pwm_set_duty(PWM_CH_LED4, 0);
+
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/draco/sensors.c b/board/draco/sensors.c
new file mode 100644
index 0000000000..b68984c95c
--- /dev/null
+++ b/board/draco/sensors.c
@@ -0,0 +1,151 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "adc.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "temp_sensor/thermistor.h"
+
+/* ADC configuration */
+struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_AMBIENT] = {
+		.name = "TEMP_AMBIENT",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_WWAN] = {
+		.name = "TEMP_WWAN",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "DDR and SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
+	},
+	[TEMP_SENSOR_2_AMBIENT] = {
+		.name = "Ambient",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_2_AMBIENT,
+	},
+	[TEMP_SENSOR_3_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_3_CHARGER,
+	},
+	[TEMP_SENSOR_4_WWAN] = {
+		.name = "WWAN",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_4_WWAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+#define THERMAL_CPU \
+	{ \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+#define THERMAL_AMBIENT \
+	{ \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ambient =
+	THERMAL_AMBIENT;
+
+/*
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 125C, max absolute temperature 150C
+ * PP3300 regulator: operating range -40 C to 125 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+#define THERMAL_CHARGER \
+	{ \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(105), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(120), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(65), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+#define THERMAL_WWAN \
+	{ \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(130), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(130), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(100), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_wwan =
+	THERMAL_WWAN;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_AMBIENT] = THERMAL_AMBIENT,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+	[TEMP_SENSOR_4_WWAN] = THERMAL_WWAN,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/draco/usbc_config.c b/board/draco/usbc_config.c
new file mode 100644
index 0000000000..1475e1f536
--- /dev/null
+++ b/board/draco/usbc_config.c
@@ -0,0 +1,367 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "cbi.h"
+#include "charger.h"
+#include "charge_ramp.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			 TCPC_FLAGS_CONTROL_VCONN,
+	},
+	[USBC_PORT_C2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		/* Compatible with Silicon Mitus SM536A0 */
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
+		.drv = &nx20p348x_drv,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux usbc0_tcss_usb_mux = {
+	.usb_port = USBC_PORT_C0,
+	.driver = &virtual_usb_mux_driver,
+	.hpd_update = &virtual_hpd_update,
+};
+static const struct usb_mux usbc2_tcss_usb_mux = {
+	.usb_port = USBC_PORT_C2,
+	.driver = &virtual_usb_mux_driver,
+	.hpd_update = &virtual_hpd_update,
+};
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set
+ * to the virtual_usb_mux_driver so the AP gets notified of mux changes
+ * and updates the TCSS configuration on state changes.
+ */
+static const struct usb_mux usbc1_usb3_db_retimer = {
+	.usb_port = USBC_PORT_C1,
+	.driver = &tcpci_tcpm_usb_mux_driver,
+	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+};
+
+const struct usb_mux usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.usb_port = USBC_PORT_C0,
+		.driver = &virtual_usb_mux_driver,
+		.hpd_update = &virtual_hpd_update,
+		.next_mux = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.usb_port = USBC_PORT_C1,
+		.driver = &virtual_usb_mux_driver,
+		.hpd_update = &virtual_hpd_update,
+		.next_mux = &usbc1_usb3_db_retimer,
+	},
+	[USBC_PORT_C2] = {
+		.usb_port = USBC_PORT_C2,
+		.driver = &virtual_usb_mux_driver,
+		.hpd_update = virtual_hpd_update,
+		.next_mux = &usbc2_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
+			port, voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+void config_usb_db_type(void)
+{
+	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
+
+	CPRINTS("Configured USB DB type number is %d", db_type);
+}
+
+void board_reset_pd_mcu(void)
+{
+	enum gpio_signal tcpc_rst;
+
+	tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL;
+
+	gpio_set_level(tcpc_rst, 0);
+	if (ec_cfg_usb_db_type() != DB_USB_ABSENT) {
+		gpio_set_level(GPIO_USB_C1_RST_ODL, 0);
+		gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
+	}
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(tcpc_rst, 1);
+	if (ec_cfg_usb_db_type() != DB_USB_ABSENT) {
+		gpio_set_level(GPIO_USB_C1_RST_ODL, 1);
+		gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
+	}
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL);
+
+	if (ec_cfg_usb_db_type() != DB_USB_ABSENT) {
+		gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+		gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+		gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
+
+	if ((ec_cfg_usb_db_type() != DB_USB_ABSENT) &&
+	    gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if ((port == USBC_PORT_C1) &&
+		 (ec_cfg_usb_db_type() != DB_USB_ABSENT))
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C2)
+		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C2_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		if (ec_cfg_usb_db_type() == DB_USB_ABSENT)
+			break;
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		if (ec_cfg_usb_db_type() == DB_USB_ABSENT)
+			break;
+		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C2_BC12_INT_ODL:
+		task_set_event(TASK_ID_USB_CHG_P2, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		switch (ec_cfg_usb_db_type()) {
+		case DB_USB_ABSENT:
+		case DB_USB_ABSENT2:
+			break;
+		case DB_USB3_PS8815:
+			nx20p348x_interrupt(USBC_PORT_C1);
+			break;
+		}
+		break;
+	case GPIO_USB_C2_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C2);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	return false;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/draco/usbc_config.h b/board/draco/usbc_config.h
new file mode 100644
index 0000000000..512580d704
--- /dev/null
+++ b/board/draco/usbc_config.h
@@ -0,0 +1,22 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Draco board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT	3
+
+enum usbc_port {
+	USBC_PORT_C0 = 0,
+	USBC_PORT_C1,
+	USBC_PORT_C2,
+	USBC_PORT_COUNT
+};
+
+void config_usb_db_type(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/draco/vif_override.xml b/board/draco/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/draco/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->