diff options
| author | Scott Collyer <scollyer@google.com> | 2021-02-16 03:21:52 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-24 23:33:07 +0000 |
| commit | 1403ddcbbdea6a55db88465659af5f0cc79ace82 (patch) | |
| tree | 73848b7f4a459d28f0f030e2a0a9a1f4231e0c06 /board/gingerbread | |
| parent | 774ff171f1ff84e7f3daa2f367b9563e00656488 (diff) | |
| download | chrome-ec-1403ddcbbdea6a55db88465659af5f0cc79ace82.tar.gz | |
honeybuns: P1 changes (gingerbread/quiche)
This CL updates both quiche and gingerbread to P1 hardware level. This
includes an MCU with 256 kB flash, some GPIO pin assignments to
address EXTi conflicts, and removing the I2C2 port.
BUG=b:183288657
BRANCH=None
TEST=make BOARD=quiche and make BOARD=gingerbread
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I6a5d3d365b6c9ed704ced8506fa4a97ca7b668c7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2699454
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'board/gingerbread')
| -rw-r--r-- | board/gingerbread/build.mk | 2 | ||||
| -rw-r--r-- | board/gingerbread/gpio.inc | 44 |
2 files changed, 35 insertions, 11 deletions
diff --git a/board/gingerbread/build.mk b/board/gingerbread/build.mk index bd3691f95a..f994cc1434 100644 --- a/board/gingerbread/build.mk +++ b/board/gingerbread/build.mk @@ -12,7 +12,7 @@ CHIP:=stm32 # codebase. Currently, using a variant of the F family so the project will # build properly. CHIP_FAMILY:=stm32g4 -CHIP_VARIANT:=stm32g431xb +CHIP_VARIANT:=stm32g473xc BASEBOARD:=honeybuns board-y=board.o diff --git a/board/gingerbread/gpio.inc b/board/gingerbread/gpio.inc index 9c590d7615..e3bb4e2ad4 100644 --- a/board/gingerbread/gpio.inc +++ b/board/gingerbread/gpio.inc @@ -7,11 +7,16 @@ /* Declare symbolic names for all the GPIOs that we care about. * Note: Those with interrupt handlers must be declared first. */ + #ifdef SECTION_IS_RW -GPIO_INT(HOST_USBC_PPC_INT_ODL, PIN(B, 0), GPIO_INT_FALLING, ppc_interrupt) +GPIO_INT(HOST_USBC_PPC_INT_ODL, PIN(C, 1), GPIO_INT_FALLING | GPIO_PULL_UP, ppc_interrupt) +/* TODO (b/183289386): These singals are required for C0 and C1 operation. + * GPIO_INT(USBC_DP_MUX_ALERT_ODL, PIN(C, 12), GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event) + * GPIO_INT(DDI_MST_IN_HPD, PIN(C, 14), GPIO_INT_BOTH, hpd_interrupt) + */ #endif -/* Power sequencing interrupts */ +/* Power sequencing signals */ GPIO(PWR_BTN, PIN(A, 0), GPIO_INPUT) GPIO(EN_AC_JACK, PIN(A, 1), GPIO_OUT_LOW) GPIO(EN_BB, PIN(C, 0), GPIO_OUT_LOW) @@ -26,8 +31,9 @@ GPIO(STATUS_LED1, PIN(A, 2), GPIO_OUT_HIGH) GPIO(STATUS_LED2, PIN(B, 12), GPIO_OUT_HIGH) /* MST Hub signals */ -GPIO(MST_LP_CTL_L, PIN(B, 9), GPIO_ODR_LOW) +GPIO(MST_LP_CTL_L, PIN(B, 9), GPIO_OUT_LOW) GPIO(MST_RST_L, PIN(B, 3), GPIO_ODR_LOW) +GPIO(MST_HUB_LANE_SWITCH, PIN(C, 15), GPIO_OUT_HIGH) /* Display Demux signals */ GPIO(DEMUX_DUAL_DP_MODE, PIN(D, 8), GPIO_OUT_LOW) @@ -46,7 +52,29 @@ GPIO(USBC_UF_RESET_L, PIN(C, 11), GPIO_ODR_LOW) GPIO(EC_HUB1_RESET_L, PIN(E, 13), GPIO_ODR_LOW) GPIO(EC_HUB2_RESET_L, PIN(E, 14), GPIO_ODR_LOW) -/* Misc Signals */ +/* DEBUG signals */ +GPIO(DEBUG_GPIO1, PIN(B, 13), GPIO_OUT_LOW) + +/* Configure as output to enable @1.5A on USBA Ports +* USB CDP enables. */ +GPIO(USB3_A1_CDP_EN, PIN(E, 7), GPIO_OUT_LOW) +GPIO(USB3_A2_CDP_EN, PIN(E, 8), GPIO_OUT_LOW) +GPIO(USB3_P3_CDP_EN, PIN(D, 1), GPIO_OUT_LOW) +GPIO(USB3_P4_CDP_EN, PIN(E, 12), GPIO_OUT_LOW) + +/* Write protect */ +GPIO(EC_FLASH_WP_ODL, PIN(A, 3), GPIO_ODR_HIGH) +GPIO(EC_WP_L, PIN(E, 11), GPIO_INT_BOTH) + + +/* SPI Bus */ +GPIO(FLASH_SPI1_NSS, PIN(A, 4), GPIO_INT_FALLING) +GPIO(FLASH_SPI1_SCK, PIN(A, 5), GPIO_INT_BOTH) +GPIO(FLASH_SPI1_MISO, PIN(A, 6), GPIO_INT_BOTH) +GPIO(FLASH_SPI1_MOSI, PIN(A, 7), GPIO_INT_BOTH) + +/* misc signals */ +GPIO(EC_DFU_MUX_CTRL, PIN(A, 8), GPIO_OUT_HIGH) /* * I2C SCL/SDA pins. These will normally be under control of the peripheral from @@ -55,16 +83,13 @@ GPIO(EC_HUB2_RESET_L, PIN(E, 14), GPIO_ODR_LOW) */ GPIO(EC_I2C1_SCL, PIN(A, 15), GPIO_ODR_HIGH) GPIO(EC_I2C1_SDA, PIN(B, 7), GPIO_ODR_HIGH) -GPIO(EC_I2C2_SDA, PIN(A, 8), GPIO_ODR_HIGH) -GPIO(EC_I2C2_SCL, PIN(A, 9), GPIO_ODR_HIGH) GPIO(EC_I2C3_SCL, PIN(C, 8), GPIO_ODR_HIGH) GPIO(EC_I2C3_SDA, PIN(C, 9), GPIO_ODR_HIGH) UNIMPLEMENTED(EC_ENTERING_RW) -UNIMPLEMENTED(EC_WP_L) - -/* UART */ +ALTERNATE(PIN_MASK(B, 0x0C00), GPIO_ALT_USART, MODULE_UART, GPIO_PULL_UP) /* GPIOB 10-11:USART3_TX/RX */ +ALTERNATE(PIN_MASK(A, 0x00F0), 5, MODULE_SPI, 0) /* GPIOA4-7: SPI Signals */ /* I2C Ports * I2C1: SDA/SCL -> PB7/PA15 * I2C2: SDA/SCL -> PA8/PA9 @@ -72,5 +97,4 @@ UNIMPLEMENTED(EC_WP_L) */ ALTERNATE(PIN_MASK(B, 0x0080), 4, MODULE_I2C, GPIO_OPEN_DRAIN) ALTERNATE(PIN_MASK(A, 0X8000), 4, MODULE_I2C, GPIO_OPEN_DRAIN) -ALTERNATE(PIN_MASK(A, 0x0300), 4, MODULE_I2C, GPIO_OPEN_DRAIN) ALTERNATE(PIN_MASK(C, 0x0300), 8, MODULE_I2C, GPIO_OPEN_DRAIN) |