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author | Alec Berg <alecaberg@chromium.org> | 2015-10-16 11:09:47 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2015-10-19 15:15:37 -0700 |
commit | 096edc1de9a7eeb4f90b9849cff6a8667bb15d30 (patch) | |
tree | d2cc9596f9d720cee04dee79f52e057886d085ec /board/glados_pd/board.h | |
parent | cb3e0ca7865d920bd89997046641b48c040e2a36 (diff) | |
download | chrome-ec-096edc1de9a7eeb4f90b9849cff6a8667bb15d30.tar.gz |
glados_pd: reduce image size and build full RO and RW
Modify glados_pd to build a full RO and RW binary. Note
that in order to fit RO and RW into the small flash size,
this CL removes the console task and adds one-way debug
printfs to save space.
For debugging purposes, you add the console back in by
uncommenting the CONSOLE task in ec.tasklist. This will
build an RW image only that has a full console.
BUG=chrome-os-partner:41959
BRANCH=none
TEST=load on glados_pd and verify host commands from EC work
and charging with zinger works. also test that software sync
works.
Change-Id: I57895d12a1776a865aac1735aeb0aa8897f1779e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/306784
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'board/glados_pd/board.h')
-rw-r--r-- | board/glados_pd/board.h | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/board/glados_pd/board.h b/board/glados_pd/board.h index 0713997921..e24aeef4ed 100644 --- a/board/glados_pd/board.h +++ b/board/glados_pd/board.h @@ -9,6 +9,13 @@ #define __CROS_EC_BOARD_H /* + * The console task is too big to include in both RO and RW images. Therefore, + * if the console task is defined, then only build an RW image. This can be + * useful for debugging to have a full console. Otherwise, without this task, + * a full RO and RW is built with a limited one-way output console. + */ +#ifdef HAS_TASK_CONSOLE +/* * The flash size is only 32kB. * No space for 2 partitions, * put only RW at the beginning of the flash @@ -21,6 +28,7 @@ /* Fake full size if we had a RO partition */ #undef CONFIG_RW_SIZE #define CONFIG_RW_SIZE CONFIG_FLASH_SIZE +#endif /* HAS_TASK_CONSOLE */ /* 48 MHz SYSCLK clock frequency */ #define CPU_CLOCK 48000000 @@ -31,9 +39,10 @@ /* Optional features */ #define CONFIG_ADC +#undef CONFIG_ADC_WATCHDOG #define CONFIG_BOARD_PRE_INIT -#undef CONFIG_CONSOLE_HISTORY -#define CONFIG_CONSOLE_HISTORY 2 +#define CONFIG_COMMON_GPIO_SHORTNAMES +#undef CONFIG_DEBUG_ASSERT #define CONFIG_FORCE_CONSOLE_RESUME #define CONFIG_HIBERNATE #define CONFIG_HIBERNATE_WAKEUP_PINS STM32_PWR_CSR_EWUP2 @@ -43,6 +52,7 @@ #define CONFIG_I2C_SLAVE_ONLY #undef CONFIG_LID_SWITCH #define CONFIG_LOW_POWER_IDLE +#define CONFIG_LTO #define CONFIG_STM_HWTIMER32 #undef CONFIG_TASK_PROFILING #undef CONFIG_UART_TX_BUF_SIZE @@ -58,6 +68,17 @@ #define CONFIG_WATCHDOG #undef CONFIG_WATCHDOG_HELP +#ifdef HAS_TASK_CONSOLE +#undef CONFIG_CONSOLE_HISTORY +#define CONFIG_CONSOLE_HISTORY 2 + +#else +#undef CONFIG_CONSOLE_CMDHELP +#define CONFIG_DEBUG_PRINTF +#define UARTN CONFIG_UART_CONSOLE +#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE) +#endif /* HAS_TASK_CONSOLE */ + /* Use PSTATE embedded in the RO image, not in its own erase block */ #undef CONFIG_FLASH_PSTATE_BANK #undef CONFIG_FW_PSTATE_SIZE |