Halvor: Initial GPIO and CONFIG_* definitions

Update GPIO to match schematic.
First pass at CONFIG_* definitions.
Just enough [base]board.c changes to build.

BUG=none
BRANCH=none
TEST=make BOARD=halvor

Change-Id: Ic5b48581b860833e6d9e74600f807b4875862ad4
Signed-off-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2120757
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>

3 files changed, 20 insertions, 26 deletions

diff --git a/board/halvor/board.h b/board/halvor/board.h
index db400f300f..f5040aaa4f 100644
--- a/board/halvor/board.h
+++ b/board/halvor/board.h
@@ -82,11 +82,10 @@
 #define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
 #define GPIO_WP_L			GPIO_EC_WP_L
 #define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
 #define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
 
 #undef CONFIG_FANS
+#undef CONFIG_VOLUME_BUTTONS
 
 #ifndef __ASSEMBLER__
 
diff --git a/board/halvor/gpio.inc b/board/halvor/gpio.inc
index 6ebbcc93b8..5223681f3d 100644
--- a/board/halvor/gpio.inc
+++ b/board/halvor/gpio.inc
@@ -47,22 +47,19 @@ GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
 /* HDMI interrupts */
 
 /* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
 
 /* Power Sequencing Signals */
 GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-/* The EC does not buffer this signal on Volteer. */
+GPIO(EN_PPVAR_VCCIN,	       PIN(4, 3), GPIO_OUT_LOW)
+
+/* The EC does not buffer this signal on Halvor. */
 UNIMPLEMENTED(PCH_DSW_PWROK)
+UNIMPLEMENTED(EN_PP5000_A)
 
 #ifdef VOLTEER_POWER_SEQUENCE
 /* Optional power sequencing signals that are not stuffed by default */
-GPIO(EN_DRAM_VDDQ,		PIN(F, 2), GPIO_OUT_LOW)
 GPIO(EN_PP1050_STG,		PIN(C, 0), GPIO_OUT_LOW)
 GPIO(EN_PP5000_USB_AG,		PIN(A, 7), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN_AUX,	PIN(8, 1), GPIO_OUT_LOW)
 GPIO(EN_PP1050_ST_S0,		PIN(3, 4), GPIO_OUT_LOW)
 GPIO(EN_VNN_BYPASS,		PIN(B, 0), GPIO_OUT_LOW)
 GPIO(EN_DRAM_VDD1,		PIN(9, 6), GPIO_OUT_LOW)
@@ -88,19 +85,28 @@ GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
 GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
 GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
 GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-UNIMPLEMENTED(EC_PROCHOT_IN_L)
 GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
 
 GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
 
 /* USB and USBC Signals */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
+GPIO(USB_C1_RT_RST_ODL,		PIN(8, 6), GPIO_ODR_LOW)
 
 /* Don't have a load switch for retimer */
 UNIMPLEMENTED(USB_C1_LS_EN)
 /* Retimer Force Power enable is connected to AP */
 UNIMPLEMENTED(USB_C1_RT_FORCE_PWR)
 
+/* Other input pins */
+GPIO(CCD_MODE_ODL,		PIN(E, 5),  GPIO_INPUT)
+GPIO(EC_PROCHOT_IN_L,		PIN(F, 0),  GPIO_INPUT)
+GPIO(CHARGER_INT_L,		PIN(7, 3),  GPIO_INPUT)
+
+/* Other output pins */
+GPIO(EC_PPEXT_EN1,		PIN(C, 2), GPIO_OUT_HIGH)
+GPIO(EC_I2CBUFFER_EN,		PIN(9, 3), GPIO_OUT_LOW)
+GPIO(UART2_EC_RX,		PIN(7, 5), GPIO_OUT_LOW)
+
 /* Misc Signals */
 
 /*
@@ -128,7 +134,7 @@ GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
 GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
 
 /* Physical HPD pins are not needed on EC as these are configured by PMC */
-GPIO(USB_C0_DP_HPD,		PIN(F, 3), GPIO_INPUT)
+GPIO(USB_C0_DP_HPD,		PIN(C, 6), GPIO_INPUT)
 GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
 
 /* Alternate functions GPIO definitions */
@@ -142,13 +148,10 @@ ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)
 /* This selects between an LED module on the motherboard and one on the daughter
  * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
  * the same time. */
-ALTERNATE(PIN_MASK(6, BIT(0)), 0, MODULE_PWM, 0)                                     /* LED_SIDESEL_4_L */
-ALTERNATE(PIN_MASK(C, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_PWM, 0)                   /* LED_{3,2,1}_L */
+
+ALTERNATE(PIN_MASK(C, BIT(3) | BIT(4)), 0, MODULE_PWM, 0)                   /* LED_{2,1}_L */
 
 /* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
 
 /* Keyboard pins */
 #define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
@@ -158,7 +161,7 @@ ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-0
 GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
 ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
 ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
+ALTERNATE(PIN_MASK(8, 0x0C), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14-15 */
 ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
 
 /* UART */
diff --git a/board/halvor/power_sequence.c b/board/halvor/power_sequence.c
index ac244c179d..1cdf7477ca 100644
--- a/board/halvor/power_sequence.c
+++ b/board/halvor/power_sequence.c
@@ -63,11 +63,6 @@ static void board_chipset_startup(void)
 	GPIO_SET_VERBOSE(GPIO_EN_PP1800_A, 1);
 
 	/*
-	 * Power on VCCIN Aux - no delay specified, but must follow VCCPRIM_1P8
-	 */
-	GPIO_SET_VERBOSE(GPIO_EN_PPVAR_VCCIN_AUX, 1);
-
-	/*
 	 * Power on bypass rails - must be turned on after VCCIN aux
 	 *
 	 * tPCH34, maximum 50 ms from SLP_SUS# de-assertion to completion of
@@ -88,7 +83,6 @@ static void board_chipset_startup(void)
 	 * VDDQ must ramp after VPP (VDD1) for DDR4/LPDDR4 systems.
 	 */
 	GPIO_SET_VERBOSE(GPIO_EN_DRAM_VDD1, 1);
-	GPIO_SET_VERBOSE(GPIO_EN_DRAM_VDDQ, 1);
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
 
@@ -127,7 +121,6 @@ static void board_chipset_shutdown(void)
 	 *  DDR_VPP           PP1800_DRAM
 	 */
 	GPIO_SET_VERBOSE(GPIO_EN_PP1050_STG, 0);
-	GPIO_SET_VERBOSE(GPIO_EN_DRAM_VDDQ, 0);
 	GPIO_SET_VERBOSE(GPIO_EN_PP1050_ST_S0, 0);
 	GPIO_SET_VERBOSE(GPIO_EN_DRAM_VDD1, 0);
 
@@ -147,7 +140,6 @@ static void board_chipset_shutdown(void)
 	chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
 
 	GPIO_SET_VERBOSE(GPIO_EN_PP1800_A, 0);
-	GPIO_SET_VERBOSE(GPIO_EN_PPVAR_VCCIN_AUX, 0);
 	GPIO_SET_VERBOSE(GPIO_EN_VNN_BYPASS, 0);
 	GPIO_SET_VERBOSE(GPIO_EN_PP1050_BYPASS, 0);
 }