diff options
| author | Nicolas Boichat <drinkcat@chromium.org> | 2018-07-02 17:23:15 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-08-23 13:20:37 -0700 |
| commit | 6853d78b821d3e0bdfe39dcde9b031f0eab162fa (patch) | |
| tree | 94e4a5a85b6a174a54ace89048e48b68445d6293 /board/kukui/gpio.inc | |
| parent | 625acc6b7c7455b0f7c6ad49f467737ce64b37eb (diff) | |
| download | chrome-ec-6853d78b821d3e0bdfe39dcde9b031f0eab162fa.tar.gz | |
kukui: Hack away SPI1_NSS on rev0
We have an interrupt conflict between SPI1_NSS and EMMC_CMD on rev0,
let's only enable EMMC_CMD for now.
rev1 fixes the issue by tying EMMC_CMD to A15 as well.
BRANCH=none
BUG=b:110907438
TEST=make BOARD=kukui -j
Change-Id: I4d3649d5ff07c778279c832be71d74410b2d4c40
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1123660
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Yilun Lin <yllin@chromium.org>
Diffstat (limited to 'board/kukui/gpio.inc')
| -rw-r--r-- | board/kukui/gpio.inc | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/board/kukui/gpio.inc b/board/kukui/gpio.inc index 70c6b25136..c4bb6db90e 100644 --- a/board/kukui/gpio.inc +++ b/board/kukui/gpio.inc @@ -11,8 +11,6 @@ */ /* Interrupts */ -GPIO_INT(SPI1_NSS, PIN(A, 15), GPIO_INT_BOTH, - spi_event) GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event) GPIO_INT(VOLUME_UP_L, PIN(B, 10), GPIO_INT_BOTH | GPIO_PULL_UP, @@ -35,12 +33,21 @@ GPIO_INT_RW(ACCEL_INT_ODL, PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_P bmi160_interrupt) GPIO_INT(CHARGER_INT_ODL, PIN(C, 13), GPIO_INT_FALLING | GPIO_PULL_UP, rt946x_interrupt) -GPIO_INT_RO(EMMC_CMD, PIN(A, 14), GPIO_INT_FALLING, - emmc_cmd_interrupt) #if BOARD_REV == 0 +GPIO_INT_RO(EMMC_CMD, PIN(B, 15), GPIO_INT_FALLING, + emmc_cmd_interrupt) GPIO_INT_RW(SYNC_INT, PIN(A, 5), GPIO_INT_RISING | GPIO_PULL_DOWN, sync_interrupt) +/* + * rev0 has an interrupt conflict between SPI1_NSS and EMMC_CMD (PIN(x, 15)), + * let's just ignore interrupts as host command won't work anyway. + */ +GPIO(SPI1_NSS, PIN(A, 15), GPIO_INPUT) #elif BOARD_REV >= 1 +GPIO_INT_RO(EMMC_CMD, PIN(A, 14), GPIO_INT_FALLING, + emmc_cmd_interrupt) +GPIO_INT(SPI1_NSS, PIN(A, 15), GPIO_INT_BOTH, + spi_event) GPIO_INT_RW(SYNC_INT, PIN(A, 8), GPIO_INT_RISING | GPIO_PULL_DOWN, sync_interrupt) GPIO_INT(HALL_INT_L, PIN(C, 5), GPIO_INT_FALLING, |