diff options
| author | Randall Spangler <rspangler@chromium.org> | 2013-04-16 09:15:39 -0700 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-04-16 14:55:12 -0700 |
| commit | 9844e82ca8372ca71d973365b5fe7964b72c7f87 (patch) | |
| tree | 9b210c5ac74a8b823c09d04e1dfa888d49f8efb8 /board/mccroskey | |
| parent | 357e508392ca37b60ea17a9ac5725f84586aac9e (diff) | |
| download | chrome-ec-9844e82ca8372ca71d973365b5fe7964b72c7f87.tar.gz | |
Remove _OFF from GPIO register macros
This is left over from when we had a pair of macros for each GPIO
register, one which concatenated its base address name and one which
took a base address. Only the latter has survived, but its naming is
longer than it needs to be and isn't consistent with other register
banks (USART, TIM, etc.).
No code changes, just renaming macros.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I15a282fd01db2a25219970e28ce551d8dc80193f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48226
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Diffstat (limited to 'board/mccroskey')
| -rw-r--r-- | board/mccroskey/board.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/board/mccroskey/board.c b/board/mccroskey/board.c index 0f56b2ebae..2faff701dc 100644 --- a/board/mccroskey/board.c +++ b/board/mccroskey/board.c @@ -109,9 +109,9 @@ void board_config_pre_init(void) /* SPI1 on pins PA4-7 (alt. function push-pull, 10MHz) */ /* FIXME: Connected device SPI freq is fxo/2 in master mode, fxo/4 * in slave mode. fxo ranges from 12-40MHz */ - val = STM32_GPIO_CRL_OFF(GPIO_A) & ~0xffff0000; + val = STM32_GPIO_CRL(GPIO_A) & ~0xffff0000; val |= 0x99990000; - STM32_GPIO_CRL_OFF(GPIO_A) = val; + STM32_GPIO_CRL(GPIO_A) = val; #endif /* remap OSC_IN/OSC_OUT to PD0/PD1 */ @@ -134,9 +134,9 @@ void board_config_pre_init(void) * * note: see crosbug.com/p/12223 for more info */ - val = STM32_GPIO_CRH_OFF(GPIO_A) & ~0x00000ff0; + val = STM32_GPIO_CRH(GPIO_A) & ~0x00000ff0; val |= 0x00000890; - STM32_GPIO_CRH_OFF(GPIO_A) = val; + STM32_GPIO_CRH(GPIO_A) = val; } /* GPIO configuration to be done after I2C module init */ @@ -147,9 +147,9 @@ void board_i2c_post_init(int port) /* enable alt. function (open-drain) */ if (port == STM32_I2C1_PORT) { /* I2C1 is on PB6-7 */ - val = STM32_GPIO_CRL_OFF(GPIO_B) & ~0xff000000; + val = STM32_GPIO_CRL(GPIO_B) & ~0xff000000; val |= 0xdd000000; - STM32_GPIO_CRL_OFF(GPIO_B) = val; + STM32_GPIO_CRL(GPIO_B) = val; } } |