ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

13 files changed, 0 insertions, 759 deletions

diff --git a/board/nocturne_fp/OWNERS b/board/nocturne_fp/OWNERS
deleted file mode 100644
index ba92c193e0..0000000000
--- a/board/nocturne_fp/OWNERS
+++ /dev/null
@@ -1 +0,0 @@
-include ../../common/fpsensor/OWNERS
diff --git a/board/nocturne_fp/board.h b/board/nocturne_fp/board.h
deleted file mode 100644
index 1f89c631eb..0000000000
--- a/board/nocturne_fp/board.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * STM32H743 + FPC 1145 Fingerprint MCU configuration
- *
- * Alternate names that share this same board file:
- *   nocturne_fp
- *   nami_fp
- *   dartmonkey
- *   dragontalon
- */
-
-#ifndef __BOARD_H
-#define __BOARD_H
-
-#undef CONFIG_SYSTEM_UNLOCKED
-
-/*
- * These allow console commands to be flagged as restricted.
- * Restricted commands will only be permitted to run when
- * console_is_restricted() returns false.
- * See console_is_restricted's definition in board.c.
- */
-#define CONFIG_CONSOLE_COMMAND_FLAGS
-#define CONFIG_RESTRICTED_CONSOLE_COMMANDS
-
-/*
- * Flash layout: we redefine the sections offsets and sizes as we want to
- * include a rollback region, and will use RO/RW regions of different sizes.
- */
-#undef _IMAGE_SIZE
-#undef CONFIG_ROLLBACK_OFF
-#undef CONFIG_ROLLBACK_SIZE
-#undef CONFIG_FLASH_PSTATE
-#undef CONFIG_FW_PSTATE_SIZE
-#undef CONFIG_FW_PSTATE_OFF
-#undef CONFIG_SHAREDLIB_SIZE
-#undef CONFIG_RO_MEM_OFF
-#undef CONFIG_RO_STORAGE_OFF
-#undef CONFIG_RO_SIZE
-#undef CONFIG_RW_MEM_OFF
-#undef CONFIG_RW_STORAGE_OFF
-#undef CONFIG_RW_SIZE
-#undef CONFIG_EC_PROTECTED_STORAGE_OFF
-#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
-#undef CONFIG_EC_WRITABLE_STORAGE_OFF
-#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
-#undef CONFIG_WP_STORAGE_OFF
-#undef CONFIG_WP_STORAGE_SIZE
-
-#define CONFIG_SHAREDLIB_SIZE   0
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (768*1024)
-
-/* EC rollback protection block */
-#define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-#define CONFIG_ROLLBACK_SIZE (CONFIG_FLASH_BANK_SIZE * 2)
-
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE_BYTES -		\
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
-
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/*
- * We want to prevent flash readout, and use it as indicator of protection
- * status.
- */
-#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-
-/* the UART console is on USART1 */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-#define CONFIG_UART_TX_DMA
-#define CONFIG_UART_TX_DMA_PH DMAMUX1_REQ_USART1_TX
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 2048
-
-/* Optional features */
-#undef CONFIG_ADC
-#define CONFIG_CMD_IDLE_STATS
-#define CONFIG_DMA
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_FPU
-#undef CONFIG_HIBERNATE
-#define CONFIG_HOST_COMMAND_STATUS
-#undef CONFIG_I2C
-#undef CONFIG_LID_SWITCH
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
-#define CONFIG_SHA256
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_SPI
-#define CONFIG_STM_HWTIMER32
-#undef CONFIG_TASK_PROFILING
-#define CONFIG_WATCHDOG_HELP
-#define CONFIG_WP_ACTIVE_HIGH
-#define CONFIG_PANIC_STRIP_GPR
-
-/* SPI configuration for the fingerprint sensor */
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FP_PORT  2 /* SPI4: third master config */
-
-#define CONFIG_FINGERPRINT_MCU
-#ifdef SECTION_IS_RW
-#define CONFIG_FP_SENSOR_FPC1145
-#define CONFIG_CMD_FPSENSOR_DEBUG
-/*
- * Use the malloc code only in the RW section (for the private library),
- * we cannot enable it in RO since it is not compatible with the RW verification
- * (shared_mem_init done too late).
- */
-#define CONFIG_MALLOC
-/* Special memory regions to store large arrays */
-#define FP_FRAME_SECTION    __SECTION(ahb4)
-#define FP_TEMPLATE_SECTION __SECTION(ahb)
-
-#else /* SECTION_IS_RO */
-/* RO verifies the RW partition signature */
-#define CONFIG_RSA
-#define CONFIG_RWSIG
-#endif
-
-#define CONFIG_RSA_KEY_SIZE 3072
-#define CONFIG_RSA_EXPONENT_3
-#define CONFIG_RWSIG_TYPE_RWSIG
-
-/* RW does slow compute, RO does slow flash erase. */
-#undef CONFIG_WATCHDOG_PERIOD_MS
-#define CONFIG_WATCHDOG_PERIOD_MS 10000
-
-/*
- * Add rollback protection
- */
-#define CONFIG_ROLLBACK
-#define CONFIG_ROLLBACK_SECRET_SIZE 32
-
-#define CONFIG_ROLLBACK_MPU_PROTECT
-
-/*
- * We do not use any "locally" generated entropy: this is normally used
- * to add local entropy when the main source of entropy is remote.
- */
-#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
-#ifdef SECTION_IS_RW
-#undef CONFIG_ROLLBACK_UPDATE
-#endif
-
-#define CONFIG_AES
-#define CONFIG_AES_GCM
-
-#define CONFIG_RNG
-
-#define CONFIG_CMD_FLASH
-
-#ifdef SECTION_IS_RW
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_CMD_SPI_XFER
-#endif
-
-#ifdef SECTION_IS_RW
-/*
- * Mitigating the effects of b/146428434.
- */
-#define APPLY_RESET_LOOP_FIX
-#endif
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_WATCHDOG 16
-
-#include "gpio_signal.h"
-#include "board_rw.h"
-
-void slp_event(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __BOARD_H */
diff --git a/board/nocturne_fp/board_ro.c b/board/nocturne_fp/board_ro.c
deleted file mode 100644
index 7f20002435..0000000000
--- a/board/nocturne_fp/board_ro.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Meowth Fingerprint MCU configuration */
-
-#include "common.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-
-#ifndef SECTION_IS_RO
-#error "This file should only be built for RO."
-#endif
-
-
-/**
- * Disable restricted commands when the system is locked.
- *
- * @see console.h system.c
- */
-int console_is_restricted(void)
-{
-	return system_is_locked();
-}
-
-#include "gpio_list.h"
-
-static void ap_deferred(void)
-{
-	/*
-	 * Behavior:
-	 * AP Active  (ex. Intel S0):   SLP_L is 1
-	 * AP Suspend (ex. Intel S0ix): SLP_L is 0
-	 * The alternative SLP_ALT_L should be pulled high at all the times.
-	 *
-	 * Legacy Intel behavior:
-	 * in S3:   SLP_ALT_L is 0 and SLP_L is X.
-	 * in S0ix: SLP_ALT_L is X and SLP_L is 0.
-	 * in S0:   SLP_ALT_L is 1 and SLP_L is 1.
-	 * in S5/G3, the FP MCU should not be running.
-	 */
-	int running = gpio_get_level(GPIO_SLP_ALT_L) &&
-		      gpio_get_level(GPIO_SLP_L);
-
-	if (running) { /* AP is S0 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_RESUME);
-	} else { /* AP is suspend/S0ix/S3 */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		enable_sleep(SLEEP_MASK_AP_RUN);
-	}
-}
-DECLARE_DEFERRED(ap_deferred);
-
-/* PCH power state changes */
-void slp_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&ap_deferred_data, 0);
-}
-
-void board_init(void)
-{
-	/* Enable interrupt on PCH power signals */
-	gpio_enable_interrupt(GPIO_SLP_ALT_L);
-	gpio_enable_interrupt(GPIO_SLP_L);
-
-	/*
-	 * Enable the SPI slave interface if the PCH is up.
-	 * Do not use hook_call_deferred(), because ap_deferred() will be
-	 * called after tasks with priority higher than HOOK task (very late).
-	 */
-	ap_deferred();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nocturne_fp/board_rw.c b/board/nocturne_fp/board_rw.c
deleted file mode 100644
index 0a7b38b97d..0000000000
--- a/board/nocturne_fp/board_rw.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "fpsensor_detect.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "board_rw.h"
-
-#ifndef SECTION_IS_RW
-#error "This file should only be built for RW."
-#endif
-
-/**
- * Disable restricted commands when the system is locked.
- *
- * @see console.h system.c
- */
-int console_is_restricted(void)
-{
-	return system_is_locked();
-}
-
-#include "gpio_list.h"
-
-/* SPI devices */
-struct spi_device_t spi_devices[] = {
-	/* Fingerprint sensor (SCLK at 4Mhz) */
-	{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = GPIO_SPI4_NSS }
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/* Allow changing the signal used for alt sleep depending on the board being
- * used: http://b/179946521.
- */
-static int gpio_slp_alt_l = GPIO_SLP_ALT_L;
-
-static void ap_deferred(void)
-{
-	/*
-	 * Behavior:
-	 * AP Active  (ex. Intel S0):   SLP_L is 1
-	 * AP Suspend (ex. Intel S0ix): SLP_L is 0
-	 * The alternative SLP_ALT_L should be pulled high at all the times.
-	 *
-	 * Legacy Intel behavior:
-	 * in S3:   SLP_ALT_L is 0 and SLP_L is X.
-	 * in S0ix: SLP_ALT_L is X and SLP_L is 0.
-	 * in S0:   SLP_ALT_L is 1 and SLP_L is 1.
-	 * in S5/G3, the FP MCU should not be running.
-	 */
-	int running = gpio_get_level(gpio_slp_alt_l) &&
-		      gpio_get_level(GPIO_SLP_L);
-
-	if (running) { /* AP is S0 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_RESUME);
-	} else { /* AP is suspend/S0ix/S3 */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		enable_sleep(SLEEP_MASK_AP_RUN);
-	}
-}
-DECLARE_DEFERRED(ap_deferred);
-
-/* PCH power state changes */
-void slp_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&ap_deferred_data, 0);
-}
-
-static void spi_configure(enum fp_sensor_spi_select spi_select)
-{
-	if (spi_select == FP_SENSOR_SPI_SELECT_DEVELOPMENT) {
-		/* SPI4 master to sensor: PE12/13/14 (CLK/MISO/MOSI) */
-		gpio_set_flags_by_mask(GPIO_E, 0x7000, 0);
-		gpio_set_alternate_function(GPIO_E, 0x7000, GPIO_ALT_SPI);
-	} else {
-		gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-	}
-
-	/* Set all SPI master signal pins to very high speed: pins E2/4/5/6 */
-	STM32_GPIO_OSPEEDR(GPIO_E) |= 0x00003f30;
-	/* Enable clocks to SPI4 module (master) */
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI4;
-
-	if (spi_select == FP_SENSOR_SPI_SELECT_DEVELOPMENT)
-		spi_devices[0].gpio_cs = GPIO_SPI4_ALT_NSS;
-	spi_enable(&spi_devices[0], 1);
-}
-
-void board_init(void)
-{
-	enum fp_sensor_spi_select spi_select = get_fp_sensor_spi_select();
-
-	/*
-	 * FP_RST_ODL pin is defined in gpio_rw.inc (with GPIO_OUT_HIGH
-	 * flag) but not in gpio.inc, so RO leaves this pin set to 0 (reset
-	 * default), but RW doesn't initialize this pin to 1 because sysjump
-	 * to RW is a warm reset (see gpio_pre_init() in chip/stm32/gpio.c).
-	 * Explicitly reset FP_RST_ODL pin to default value.
-	 */
-	gpio_reset(GPIO_FP_RST_ODL);
-
-	ccprints("FP_SPI_SEL: %s", fp_sensor_spi_select_to_str(spi_select));
-
-	spi_configure(spi_select);
-
-	ccprints("TRANSPORT_SEL: %s",
-		 fp_transport_type_to_str(get_fp_transport_type()));
-
-	/* Use SPI select as a proxy for running on the icetower dev board. */
-	if (spi_select == FP_SENSOR_SPI_SELECT_DEVELOPMENT)
-		gpio_slp_alt_l = GPIO_SLP_ALT_DEV_L;
-
-	/* Enable interrupt on PCH power signals */
-	gpio_enable_interrupt(gpio_slp_alt_l);
-	gpio_enable_interrupt(GPIO_SLP_L);
-
-	/*
-	 * Enable the SPI slave interface if the PCH is up.
-	 * Do not use hook_call_deferred(), because ap_deferred() will be
-	 * called after tasks with priority higher than HOOK task (very late).
-	 */
-	ap_deferred();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nocturne_fp/board_rw.h b/board/nocturne_fp/board_rw.h
deleted file mode 100644
index 6ef7cc29b4..0000000000
--- a/board/nocturne_fp/board_rw.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_BOARD_NOCTURNE_FP_BOARD_RW_H
-#define __CROS_EC_BOARD_NOCTURNE_FP_BOARD_RW_H
-
-void fps_event(enum gpio_signal signal);
-
-/* Defined in ro_workarounds.c */
-void wp_event(enum gpio_signal signal);
-
-#endif /* __CROS_EC_BOARD_NOCTURNE_FP_BOARD_RW_H */
diff --git a/board/nocturne_fp/build.mk b/board/nocturne_fp/build.mk
deleted file mode 100644
index 2091acc101..0000000000
--- a/board/nocturne_fp/build.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32H743
-CHIP:=stm32
-CHIP_FAMILY:=stm32h7
-CHIP_VARIANT:=stm32h7x3
-
-# Don't forget that the board build.mk is included more than once to allow
-# conditional variables to be realized. This means that we need to redefine all
-# variable or the "+=" lines will compound.
-board-y=
-board-rw=ro_workarounds.o board_rw.o
-board-ro=board_ro.o
-# If we're mocking the sensor detection for testing (so we can test
-# sensor/transport permutations in the unit tests), don't build the real sensor
-# detection.
-ifeq ($(HAS_MOCK_FPSENSOR_DETECT),)
-	board-rw+=fpsensor_detect_rw.o
-	board-y+=fpsensor_detect.o
-endif
-
-# Do not build rsa test because this board uses RSA exponent 3 and the rsa test
-# will fail on device.
-test-list-y=\
-       aes \
-       cec \
-       compile_time_macros \
-       crc \
-       flash_physical \
-       flash_write_protect \
-       fpsensor \
-       fpsensor_hw \
-       mpu \
-       mutex \
-       pingpong \
-       printf \
-       queue \
-       rollback \
-       rollback_entropy \
-       rsa3 \
-       rtc \
-       scratchpad \
-       sha256 \
-       sha256_unrolled \
-       static_if \
-       timer_dos \
-       utils \
-       utils_str \
diff --git a/board/nocturne_fp/dev_key.pem b/board/nocturne_fp/dev_key.pem
deleted file mode 100644
index 35c0035b20..0000000000
--- a/board/nocturne_fp/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4wIBAAKCAYEAoxINZU5fQAiABFm4xT83HUQx/WvRlyZ3ZfRqTyMlMxw7U0cU
-DEw7fOY0oj20bkpmVJRfwkm4k7BwOuTt3nl5UuKgeztL4gW+h++ptIIzfT2/a4KL
-BnHsuNfgXZ+yzJ5RSKlJwVOibJr5CNfsmESX4Lwe3LudFc7iE/yfgsOyU/9Ha/jB
-mgLywyWObwpfAt+viOCIF4mYeEI5bLpDHqwk6EnEq0jWaNpcEsLA/twhDf2Qxc7I
-7Zds3f6C3iA1N/d0Zmva4UvdAGnFzQlq9mmgnCenIjwEb4jxqcFXaMgk88jkcheY
-q7MQANRt+iYOX2MiUNtigUoDoJTMBiV3bRs47sSiH+lS6hZHdOsmjMyF30bV5IJD
-k+x1Zoxsd2jYR1PXgxZ+pxLoKx/m9KIV8onbqgl0Jx4+JkABH5eYp/KAhObCenLS
-CySFi7OLbi915yydzFJ3C34pgWVN077GVCXGqglxDcNMacqXqHCwOUoNuAGXjxyF
-XH33G9a/TJDzQhZFAgEDAoIBgGy2s5je6iqwVVg70IN/ehOCy/5H4Q9u+kP4Rt9s
-w3doJ4zaDV2IJ6iZeGwpIvQxmY24P9bb0GJ1oCdDST77pjdBwFInh+wD1FqfxnhW
-zP4pKkesXK72ndCP6ukVId2+4NsbhoDibEhnULCP8xAtupXSvz3SaLk0lrf9v6yC
-duKqL51QgRFXTIIZCZ9cP1c/yltAWrpbuvrW0PMm12nIGJrb2HIwjvCRkrcsgKno
-FglTtdk0hfO6SJP/AelqziVPod5DxP4Gcws0JWnWjIKtYmNpIrI/sfVD29DNLYYS
-Pn1Vgxi5UcwfEbcxkwxMKoJOUb1WSPkvjpQTlQUPiBLX3sLpLvxaOVrEjNXy+V13
-Jl7bc2dGbDIsQMXkFiodTHsqwAq1diFOUL9oE6VeES2hmX63f7lHSXMb92phmvs4
-BylzoTK64ew8oUkufLTX/ys0LGiGvPXCrdfDxdsO2Rx90XB5YPcvvQKge0eCfDck
-kCX4C/6j7V3y/nS5GzpLCFshqwKBwQDVaKdjlpzAKKu+hfBRaujZsrgXd2i4LTuI
-r+sclHl4aII0HJbSolsiV8Pc+jcFtvzLDUnSh4Pjza/6qtYF0q3fxAXQCmBAq8Xc
-AF2sYmZJmMT4OajMS0LG7nhYgm5OpXpyvgc+ndBnDtqXVPQy/wpo8dBV8G1QtXbj
-OsvrTeQ8ZaFcUA4jOuyz+VNpONOUzvxx/jVwuEDVl7xB5/6TayNbCrecqd6CsSur
-S3Z21lelrCV/CjIJqkPZQlgwsKE31CUCgcEAw52MAKuTr3Lh78Gn4PqkLVc6/2UQ
-x3XsZ92oAxhNv2AdmOUHJuIaS7JNirmXljaq6cyrOPsp3qm8g+NVSwS86qLV1Vec
-oUOuV/5S1DdmB2Tj0V74fF7RdsfS37p3P+49AEhGNn+epPTu5UAH+xhrAwRkO0Li
-qOCXHMpkQ9CRilOvUgpxBY6m6fR89bKjkY9evYomKiHj6CfoyUCCFf3pJkin/lHS
-YyizEeF/b7zd2WFgEhxvRec1k36+RG/FgY+hAoHBAI5FxO0PEyrFx9RZSuDx8JEh
-0A+k8HrI0lsf8hMNplBFrCK9ueHBkhblLT38JK55/dyzhoxaV+0zyqccjq6Mc+qC
-roqxlYByg+gAPnLsRDEQg1AmcIgyLISe+uWsSYnDpvcpWim+iu9fPGTjTXdUsZtL
-4DlK84sjpJd8h/Iz7X2ZFj2KtBd8nc1Q4kYl4mM0qEv+zkslgI5lKCvv/wzyF5IH
-JRMb6ax2HRzc+aSO5RkdblSxdrEcLTuBkCB1wM/iwwKBwQCCaQgAcmJ090FKgRqV
-/G1zj3yqQ2CE+UhFPnACEDPU6r5l7gTElrwydt5ce7pkJHHxMxzQp3E/G9MCl44y
-AyicbI6OOmhrgnQ6qYyNekQE7e02P1BS6eD52oyVJvoqntNVhYQkVRRt+J9DgAVS
-EEdXWELSLJcbQGS93ELX4GEG4nThXEtZCcSb+FNOdxe2X5R+XBlxa+1Fb/CGKwFj
-/ptu2xqpi+GXcHdhQP+f0z6Q65VhaEoumiO3qdQtn9kBCmsCgcEA0/VwBz03FMcv
-2SM6zDbL2Kf4PnnLJuDHFzItWH8smrBNVfOOuJ5KGhuIHAAJxaQoWBxeYeaPPqme
-5rQRl58XEb5h3FswAKPx2U77NUROtObOVffV5Tid1E+iBQYhlUUkxtE5b+Said3u
-LqkP8K5n1ai2xuvHusuL6vcp/5T+WrSG5GDiGU+27c2Uf/NePbFYggLl3P9rmDM8
-/1xGGpxMGV2OrOhXtPk7LykEdJRuN+7YhNX5dW1LwWcicOLkFVOG
------END RSA PRIVATE KEY-----
diff --git a/board/nocturne_fp/ec.tasklist b/board/nocturne_fp/ec.tasklist
deleted file mode 100644
index ed1e6ed294..0000000000
--- a/board/nocturne_fp/ec.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \
-	TASK_ALWAYS_RW(FPSENSOR, fp_task, NULL, 4096) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 4096) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE)
diff --git a/board/nocturne_fp/fpsensor_detect.c b/board/nocturne_fp/fpsensor_detect.c
deleted file mode 100644
index 5a4b95e64c..0000000000
--- a/board/nocturne_fp/fpsensor_detect.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "fpsensor_detect.h"
-
-enum fp_transport_type get_fp_transport_type(void)
-{
-	return FP_TRANSPORT_TYPE_SPI;
-}
diff --git a/board/nocturne_fp/fpsensor_detect_rw.c b/board/nocturne_fp/fpsensor_detect_rw.c
deleted file mode 100644
index e4a670e211..0000000000
--- a/board/nocturne_fp/fpsensor_detect_rw.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "fpsensor_detect.h"
-#include "gpio.h"
-#include "timer.h"
-
-enum fp_sensor_type get_fp_sensor_type(void)
-{
-	return FP_SENSOR_TYPE_FPC;
-}
-
-enum fp_sensor_spi_select get_fp_sensor_spi_select(void)
-{
-	enum fp_sensor_spi_select ret;
-
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
-	usleep(1);
-	switch (gpio_get_level(GPIO_FP_SPI_SEL)) {
-	case 0:
-		ret = FP_SENSOR_SPI_SELECT_DEVELOPMENT;
-		break;
-	case 1:
-		ret = FP_SENSOR_SPI_SELECT_PRODUCTION;
-		break;
-	default:
-		ret = FP_SENSOR_SPI_SELECT_UNKNOWN;
-		break;
-	}
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 0);
-	return ret;
-}
diff --git a/board/nocturne_fp/gpio.inc b/board/nocturne_fp/gpio.inc
deleted file mode 100644
index dc15ab0ef0..0000000000
--- a/board/nocturne_fp/gpio.inc
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupts */
-GPIO_INT(SLP_L,           PIN(D,13), GPIO_INT_BOTH, slp_event)
-GPIO_INT(SLP_ALT_L,       PIN(A,11), GPIO_INT_BOTH, slp_event)
-GPIO_INT(SPI1_NSS,        PIN(A, 4), GPIO_INPUT, spi_event)
-
-/* Inputs */
-#ifndef APPLY_RESET_LOOP_FIX
-GPIO(WP,                  PIN(B, 7), GPIO_INPUT)
-#endif
-
-/* Outputs */
-GPIO(EC_INT_L,            PIN(A, 1),  GPIO_OUT_HIGH)
-
-UNIMPLEMENTED(ENTERING_RW)
-
-/* USART1: PA9/PA10 (TX/RX) */
-ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
-/* SPI1 slave from the AP: PA4/5/6/7 (CS/CLK/MISO/MOSI) */
-ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI,  0)
-
-#ifdef SECTION_IS_RW
-#include "gpio_rw.inc"
-#endif
diff --git a/board/nocturne_fp/gpio_rw.inc b/board/nocturne_fp/gpio_rw.inc
deleted file mode 100644
index 2de4c3e92a..0000000000
--- a/board/nocturne_fp/gpio_rw.inc
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef SECTION_IS_RW
-#error "This file should only be included in RW."
-#endif
-
-/* Interrupts */
-GPIO_INT(FPS_INT,         PIN(A, 0), GPIO_INT_RISING, fps_event)
-
-#ifdef APPLY_RESET_LOOP_FIX
-GPIO_INT(WP,              PIN(B, 7), GPIO_INT_BOTH, wp_event)
-#endif
-
-/* Inputs */
-GPIO_INT(SLP_ALT_DEV_L,   PIN(D,14), GPIO_INT_BOTH, slp_event)
-/*
- * The S4 and SUS sleep lines are unused in code, but are maintained in this
- * gpio list to ensure that they are not repurposed. This is because these
- * inputs are driven on nocturne.
- */
-GPIO(PCH_SLP_S4_L,        PIN(D, 8), GPIO_INPUT)
-GPIO(PCH_SLP_SUS_L,       PIN(D, 3), GPIO_INPUT)
-/* TODO(b/178808871): Only enable pull up when doing detection. */
-GPIO(FP_SPI_SEL,          PIN(E, 1), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Outputs */
-GPIO(DIVIDER_HIGHSIDE,    PIN(B, 8),  GPIO_OUT_LOW)
-GPIO(FP_RST_ODL,          PIN(E, 0),  GPIO_OUT_HIGH)
-GPIO(SPI4_NSS,            PIN(E, 4),  GPIO_OUT_HIGH)
-GPIO(SPI4_ALT_NSS,        PIN(E, 11), GPIO_OUT_HIGH)
-GPIO(USER_PRES_L,         PIN(C, 5),  GPIO_ODR_HIGH)
-
-/* Default SPI4 master to sensor: PE2/5/6 (CLK/MISO/MOSI) */
-ALTERNATE(PIN_MASK(E, 0x0064), GPIO_ALT_SPI, MODULE_SPI_CONTROLLER,  0)
-
-/* See board_rw.c for the alternate configuration that we use on
- * development boards, which overrides the UNUSED values below.
- */
-UNUSED(PIN(E, 12))  /* Alternate SPI4 master to sensor CLK */
-UNUSED(PIN(E, 13))  /* Alternate SPI4 master to sensor MISO */
-UNUSED(PIN(E, 14))  /* Alternate SPI4 master to sensor MOSI */
diff --git a/board/nocturne_fp/ro_workarounds.c b/board/nocturne_fp/ro_workarounds.c
deleted file mode 100644
index e980d14877..0000000000
--- a/board/nocturne_fp/ro_workarounds.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* A place to organize workarounds for legacy RO */
-
-#include <assert.h>
-#include <stdbool.h>
-
-#include "bkpdata.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h" /* Reset cause */
-#include "gpio.h"
-#include "hooks.h"
-#include "system.h"
-#include "task.h"
-#include "watchdog.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-/*
- * We only patch RW to ensure that future ROs have correct behavior.
- */
-#if defined(APPLY_RESET_LOOP_FIX) && defined(SECTION_IS_RW)
-
-/*
- * Add in ap-off flag to be able to detect on next boot.
- * No other code in this build uses this ap-off reset flag.
- */
-#define FORGE_PORFLAG_FLAGS (EC_RESET_FLAG_POWER_ON|EC_RESET_FLAG_AP_OFF)
-
-static void wp_change_deferred(void)
-{
-	/*
-	 * The normal state of the reset backup register is 0, but
-	 * we know that our override version of bkpdata_write_reset_flags
-	 * will adjust it based on GPIO_WP's status.
-	 */
-	bkpdata_write_reset_flags(0);
-}
-DECLARE_DEFERRED(wp_change_deferred);
-
-/*
- * We respond to changes in the hardware write protect line in order to
- * ensure this workaround is installed when it is needed and uninstalled
- * when it is not needed. This ensures that we are protected during
- * unexpected resets, such as pin resets or double faults.
- *
- * Furthermore, installing and uninstalling when needed minimizes the
- * difference between our normal operating conditions and normal operating
- * conditions with this ro_workaround source being included. That is to say,
- * the system behavior is only altered in the less likely state, when hardware
- * write protect deasserted.
- */
-void wp_event(enum gpio_signal signal)
-{
-	/*
-	 * We must use a deferred function to call bkpdata_write_reset_flags,
-	 * since the underlying bkpdata_write uses a mutex.
-	 */
-	hook_call_deferred(&wp_change_deferred_data, 0);
-}
-
-/*
- * We intercept all changes to the reset backup register to ensure that
- * our reset loop patch stays in place.
- *
- * This function will be called once in check_reset_cause during
- * startup, which ensures proper behavior even when unexpected
- * resets occurs (pin reset or exception).
- *
- * This function is also called from system_reset to set the final save
- * reset flags, before an actual planned reset.
- */
-__override
-void bkpdata_write_reset_flags(uint32_t save_flags)
-{
-	/* Preserve flags in case a reset pulse occurs */
-	if (!gpio_get_level(GPIO_WP))
-		save_flags |= FORGE_PORFLAG_FLAGS;
-
-	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags & 0xffff);
-	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS_2, save_flags >> 16);
-}
-
-/*
- * We do not need to explicitly invoke bkpdata_write_reset_flags
- * on boot, since check_reset_cause will already invoke it once on boot.
- */
-static void board_init_workarounds(void)
-{
-	gpio_disable_interrupt(GPIO_WP);
-	gpio_clear_pending_interrupt(GPIO_WP);
-
-	/*
-	 * Detect our forged power-on flag and correct the current
-	 * system reset flags.
-	 * This does not ensure that all init functions will see
-	 * the corrected system reset flags, so care should be taken.
-	 */
-	if ((system_get_reset_flags() & FORGE_PORFLAG_FLAGS) ==
-	    FORGE_PORFLAG_FLAGS) {
-		CPRINTS("WARNING: Reset flags power-on + ap-off were forged.");
-		system_clear_reset_flags(FORGE_PORFLAG_FLAGS);
-	}
-
-	gpio_enable_interrupt(GPIO_WP);
-}
-/* Run one priority level higher than the main board_init in board.c */
-DECLARE_HOOK(HOOK_INIT, board_init_workarounds, HOOK_PRIO_DEFAULT - 1);
-
-#endif /* APPLY_RESET_LOOP_FIX && SECTION_IS_RW */