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| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-06-27 13:56:32 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-07-01 21:20:04 +0000 |
| commit | 19efefd1c39785d6042f9e8998259a1ae4bd0d65 (patch) | |
| tree | 3234ce479990ea93b6f4d2dfca743e751248b470 /board/npcx9_evb | |
| parent | 45239a4cb30caeec1079c8843b9e5d7beed94d89 (diff) | |
| download | chrome-ec-19efefd1c39785d6042f9e8998259a1ae4bd0d65.tar.gz | |
board/npcx9_evb/board.h: Format with clang-format
BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: Id895ddcf236a3d2e44f152e243c0558134fde9c6
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728768
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Diffstat (limited to 'board/npcx9_evb')
| -rw-r--r-- | board/npcx9_evb/board.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/board/npcx9_evb/board.h b/board/npcx9_evb/board.h index a0d209c938..e707c0258e 100644 --- a/board/npcx9_evb/board.h +++ b/board/npcx9_evb/board.h @@ -25,9 +25,9 @@ #define CONFIG_I2C_CONTROLLER #define CONFIG_KEYBOARD_PROTOCOL_8042 -#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */ +#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */ #define CONFIG_POWER_BUTTON -#undef CONFIG_PSTORE +#undef CONFIG_PSTORE #define CONFIG_PWM_KBLIGHT #define CONFIG_VBOOT_HASH #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */ @@ -43,14 +43,14 @@ /* I2C port for CONFIG_CMD_I2CWEDGE */ #define I2C_PORT_MASTER NPCX_I2C_PORT0_0 -#define I2C_PORT_HOST 0 +#define I2C_PORT_HOST 0 /* Fans for testing */ #define CONFIG_FANS 1 #define CONFIG_TEMP_SENSOR #define CONFIG_TEMP_SENSOR_TMP112 -#define I2C_PORT_THERMAL NPCX_I2C_PORT2_0 +#define I2C_PORT_THERMAL NPCX_I2C_PORT2_0 #define CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Quasi-bidirectional buf for KSOs */ #define CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */ @@ -60,15 +60,15 @@ /* Select which UART Controller is the Console UART */ #undef CONFIG_CONSOLE_UART -#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */ +#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */ /* * This definition below actually doesn't define which UART controller to be * used. Instead, it defines which pinouts (GPIO10/11 or GPIO64/65) are * connected to "UART1" controller. */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ -#define NPCX9_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX9_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 */ #ifndef __ASSEMBLER__ @@ -94,7 +94,7 @@ enum tmp112_sensor { }; enum temp_sensor_id { - TEMP_SENSOR_SYSTHERM0, /* TMP100 */ + TEMP_SENSOR_SYSTHERM0, /* TMP100 */ TEMP_SENSOR_COUNT }; |