diff options
author | CHLin <CHLin56@nuvoton.com> | 2020-09-28 14:17:45 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-10-07 05:16:40 +0000 |
commit | 247942fa7d1444bdbb7402d43cd1334ccf58cfeb (patch) | |
tree | bc3637f1921f7b70b690019ad38afe1e46caa7cb /board/npcx9_evb | |
parent | d9d6c27f1c765fdfc6b1f5714d0e57b3d895de44 (diff) | |
download | chrome-ec-247942fa7d1444bdbb7402d43cd1334ccf58cfeb.tar.gz |
npcx9_evb: add board to support the npcx9's EVB
Add board npcx9_evb to verify npcx9's functions.
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST=Check EC firmware can boot up the EVB; verify the functionality of
required modules (Ex: ADC/GPIO/KBC/I2C/PWM/FAN/PSL/UART.)
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I40d69bc4e698a03dc2229bb2eaea8e25ca090867
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435166
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Diffstat (limited to 'board/npcx9_evb')
-rw-r--r-- | board/npcx9_evb/board.c | 129 | ||||
-rw-r--r-- | board/npcx9_evb/board.h | 110 | ||||
-rw-r--r-- | board/npcx9_evb/build.mk | 18 | ||||
-rw-r--r-- | board/npcx9_evb/ec.tasklist | 14 | ||||
-rw-r--r-- | board/npcx9_evb/gpio.inc | 112 |
5 files changed, 383 insertions, 0 deletions
diff --git a/board/npcx9_evb/board.c b/board/npcx9_evb/board.c new file mode 100644 index 0000000000..892c0d1031 --- /dev/null +++ b/board/npcx9_evb/board.c @@ -0,0 +1,129 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Nuvoton M4 EB board-specific configuration */ + +#include "adc.h" +#include "adc_chip.h" +#include "backlight.h" +#include "chipset.h" +#include "common.h" +#include "extpower.h" +#include "fan.h" +#include "fan_chip.h" +#include "gpio.h" +#include "i2c.h" +#include "keyboard_scan.h" +#include "lid_switch.h" +#include "peci.h" +#include "power.h" +#include "power_button.h" +#include "pwm.h" +#include "pwm_chip.h" +#include "registers.h" +#include "spi.h" +#include "switch.h" +#include "temp_sensor.h" +#include "temp_sensor_chip.h" +#include "timer.h" +#include "thermal.h" +#include "util.h" + +#include "gpio_list.h" + +/******************************************************************************/ +/* ADC channels. Must be in the exactly same order as in enum adc_channel. */ +const struct adc_t adc_channels[] = { + [ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_3] = {"ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_4] = {"ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_5] = {"ADC5", NPCX_ADC_CH5, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_6] = {"ADC6", NPCX_ADC_CH6, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_7] = {"ADC7", NPCX_ADC_CH7, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_8] = {"ADC8", NPCX_ADC_CH8, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_9] = {"ADC9", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_10] = {"ADC10", NPCX_ADC_CH10, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_11] = {"ADC11", NPCX_ADC_CH11, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, +}; +BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); + +/******************************************************************************/ +/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ +const struct pwm_t pwm_channels[] = { + [PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000}, + [PWM_CH_KBLIGHT] = { 2, 0, 10000 }, +}; +BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); + +/******************************************************************************/ +/* Physical fans. These are logically separate from pwm_channels. */ +const struct fan_conf fan_conf_0 = { + .flags = FAN_USE_RPM_MODE, + .ch = 0, /* Use MFT id to control fan */ + .pgood_gpio = GPIO_PGOOD_FAN, + .enable_gpio = -1, +}; + +const struct fan_rpm fan_rpm_0 = { + .rpm_min = 1000, + .rpm_start = 1000, + .rpm_max = 5200, +}; + +const struct fan_t fans[] = { + [FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, }, +}; +BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); + +/******************************************************************************/ +/* MFT channels. These are logically separate from pwm_channels. */ +const struct mft_t mft_channels[] = { + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, +}; +BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); + +/******************************************************************************/ +/* I2C ports */ +const struct i2c_port_t i2c_ports[] = { + {"master0-0", NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0}, + {"master1-0", NPCX_I2C_PORT1_0, 100, GPIO_I2C1_SCL0, GPIO_I2C1_SDA0}, + {"master2-0", NPCX_I2C_PORT2_0, 100, GPIO_I2C2_SCL0, GPIO_I2C2_SDA0}, + {"master3-0", NPCX_I2C_PORT3_0, 100, GPIO_I2C3_SCL0, GPIO_I2C3_SDA0}, + {"master7-0", NPCX_I2C_PORT7_0, 100, GPIO_I2C7_SCL0, GPIO_I2C7_SDA0}, +}; +const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); + +/******************************************************************************/ +/* SPI devices */ +const struct spi_device_t spi_devices[] = { + { CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L}, +}; +const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); + +/******************************************************************************/ +/* Wake-up pins for hibernate */ +const enum gpio_signal hibernate_wake_pins[] = { + GPIO_AC_PRESENT, + GPIO_LID_OPEN, + GPIO_POWER_BUTTON_L, +}; +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); + +/******************************************************************************/ +/* Keyboard scan setting */ +struct keyboard_scan_config keyscan_config = { + .output_settle_us = 40, + .debounce_down_us = 6 * MSEC, + .debounce_up_us = 30 * MSEC, + .scan_period_us = 1500, + .min_post_scan_delay_us = 1000, + .poll_timeout_us = SECOND, + .actual_key_mask = { + 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, + 0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xc8 /* full set */ + }, +}; diff --git a/board/npcx9_evb/board.h b/board/npcx9_evb/board.h new file mode 100644 index 0000000000..cac7ea99be --- /dev/null +++ b/board/npcx9_evb/board.h @@ -0,0 +1,110 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Configuration for Nuvoton M4 EB */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* EC modules */ +#define CONFIG_ADC +#define CONFIG_PWM +#define CONFIG_SPI +#define CONFIG_I2C +/* Features of eSPI */ +#define CONFIG_HOSTCMD_ESPI +#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3 +#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 + +/* Optional features */ +#define CONFIG_ENABLE_JTAG_SELECTION +#define CONFIG_BOARD_VERSION_GPIO +#define CONFIG_EXTPOWER_GPIO +#define CONFIG_I2C_MASTER +#define CONFIG_KEYBOARD_BOARD_CONFIG +#define CONFIG_KEYBOARD_PROTOCOL_8042 +#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */ +#define CONFIG_POWER_BUTTON +#undef CONFIG_PSTORE +#define CONFIG_PWM_KBLIGHT +#define CONFIG_VBOOT_HASH +#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */ + +/* EC console commands */ +#define CONFIG_CMD_TASKREADY +#define CONFIG_CMD_STACKOVERFLOW +#define CONFIG_CMD_JUMPTAGS +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_SPI_FLASH +#define CONFIG_CMD_SCRATCHPAD +#define CONFIG_CMD_I2CWEDGE + +/* I2C port for CONFIG_CMD_I2CWEDGE */ +#define I2C_PORT_MASTER NPCX_I2C_PORT0_0 +#define I2C_PORT_HOST 0 + +/* Fans for testing */ +#define CONFIG_FANS 1 + +#define CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Quasi-bidirectional buf for KSOs */ +#define CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */ +#undef CONFIG_CLOCK_SRC_EXTERNAL /* Use external 32kHz OSC as LFCLK source */ + +/* Optional feature to configure npcx9 chip */ + +/* Select which UART Controller is the Console UART */ +#undef CONFIG_CONSOLE_UART +#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */ +/* + * This definition below actually doesn't define which UART controller to be + * used. Instead, it defines which pinouts (GPIO10/11 or GPIO64/65) are + * connected to "UART1" controller. + */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX9_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 */ + +#ifndef __ASSEMBLER__ + +enum adc_channel { + ADC_CH_0 = 0, + ADC_CH_1, + ADC_CH_2, + ADC_CH_3, + ADC_CH_4, + ADC_CH_5, + ADC_CH_6, + ADC_CH_7, + ADC_CH_8, + ADC_CH_9, + ADC_CH_10, + ADC_CH_11, + ADC_CH_COUNT +}; + +enum pwm_channel { + PWM_CH_FAN, + PWM_CH_KBLIGHT, + /* Number of PWM channels */ + PWM_CH_COUNT +}; + +enum fan_channel { + FAN_CH_0, + /* Number of FAN channels */ + FAN_CH_COUNT +}; + +enum mft_channel { + MFT_CH_0, + /* Number of MFT channels */ + MFT_CH_COUNT +}; + +#include "gpio_signal.h" + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/npcx9_evb/build.mk b/board/npcx9_evb/build.mk new file mode 100644 index 0000000000..92bcc84144 --- /dev/null +++ b/board/npcx9_evb/build.mk @@ -0,0 +1,18 @@ +# -*- makefile -*- +# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build +# + +# the IC is Nuvoton NPCX9 M-Series EC (npcx9m3f, npcx9m6f) +# CHIP_VARIANT: +# npcx9m6f - for npcx9 ec with 512 KByte internal flash. +# npcx9m3f - for npcx9 ec with 512 KByte internal flash, more RAM. + +CHIP:=npcx +CHIP_FAMILY:=npcx9 +CHIP_VARIANT:=npcx9m3f + +board-y=board.o diff --git a/board/npcx9_evb/ec.tasklist b/board/npcx9_evb/ec.tasklist new file mode 100644 index 0000000000..9560b43561 --- /dev/null +++ b/board/npcx9_evb/ec.tasklist @@ -0,0 +1,14 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * See CONFIG_TASK_LIST in config.h for details. + */ +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) diff --git a/board/npcx9_evb/gpio.inc b/board/npcx9_evb/gpio.inc new file mode 100644 index 0000000000..ec57c1afc5 --- /dev/null +++ b/board/npcx9_evb/gpio.inc @@ -0,0 +1,112 @@ +/* -*- mode:c -*- + * + * Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Declare symbolic names for all the GPIOs that we care about. + * Note: Those with interrupt handlers must be declared first. */ + +/* Pins for internal flash testing */ +GPIO_INT(RECOVERY_L, PIN(0, 3), GPIO_INT_BOTH | GPIO_PULL_UP, switch_interrupt) +GPIO_INT(WP_L, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, switch_interrupt) + +/* Pins for hibernate testing */ +#ifdef CONFIG_HIBERNATE_PSL +/* + * Please notice internal PU/PD is gone if IOs are selected to PSL_INx. The + * power consumption of PSL is ultra-low and sensitive. Putting a large + * external PU/PD resistance for PSL input pins is recommended. + */ +GPIO_INT(AC_PRESENT, PIN(D, 2), GPIO_INT_BOTH, extpower_interrupt) /* PSL_IN1# (Low Active) */ +GPIO_INT(POWER_BUTTON_L, PIN(0, 0), GPIO_INT_BOTH, power_button_interrupt) /* PSL_IN2# (Low Active) */ +GPIO_INT(LID_OPEN, PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) /* PSL_IN3# (High Active) */ +#else +GPIO_INT(AC_PRESENT, PIN(7, 4), GPIO_INT_BOTH | GPIO_PULL_UP, extpower_interrupt) +GPIO_INT(POWER_BUTTON_L, PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt) +GPIO_INT(LID_OPEN, PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_DOWN, lid_interrupt) +#endif + +/* Pins for SPI/FAN/LPC modules testing */ +GPIO(ENTERING_RW, PIN(3, 6), GPIO_OUT_LOW ) +GPIO(PCH_WAKE_L, PIN(5, 0), GPIO_OUT_HIGH) +GPIO(PGOOD_FAN, PIN(C, 7), GPIO_INPUT | GPIO_PULL_UP) +GPIO(SPI_CS_L, PIN(A, 5), GPIO_OUT_HIGH) + +/* Pins for I2C module testing */ +GPIO(I2C0_SCL0, PIN(B, 5), GPIO_ODR_HIGH) +GPIO(I2C0_SDA0, PIN(B, 4), GPIO_ODR_HIGH) +GPIO(I2C1_SCL0, PIN(9, 0), GPIO_ODR_HIGH) +GPIO(I2C1_SDA0, PIN(8, 7), GPIO_ODR_HIGH) +GPIO(I2C2_SCL0, PIN(9, 2), GPIO_ODR_HIGH) +GPIO(I2C2_SDA0, PIN(9, 1), GPIO_ODR_HIGH) +GPIO(I2C3_SCL0, PIN(D, 1), GPIO_ODR_HIGH) +GPIO(I2C3_SDA0, PIN(D, 0), GPIO_ODR_HIGH) +GPIO(I2C7_SDA0, PIN(B, 2), GPIO_ODR_HIGH) +GPIO(I2C7_SCL0, PIN(B, 3), GPIO_ODR_HIGH) + +/* Pins for board version command */ +GPIO(BOARD_VERSION1, PIN(6, 4), GPIO_INPUT) +GPIO(BOARD_VERSION2, PIN(6, 5), GPIO_INPUT) +GPIO(BOARD_VERSION3, PIN(6, 6), GPIO_INPUT) + +/*********************** Alternate pins for npcx7 series **********************/ +#if (CONFIG_CONSOLE_UART == 0) +/* UART1 Tx/Rx */ +#if NPCX_UART_MODULE2 +ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0) /* CR_SIN/SOUT GPIO64/65 */ +#else +ALTERNATE(PIN_MASK(1, 0x03), 1, MODULE_UART, 0) /* CR_SIN/SOUT GPIO10/11 */ +#endif +#else +/* UART2 Tx/Rx */ +ALTERNATE(PIN_MASK(7, 0x20), 1, MODULE_UART, 0) /* CR_SIN2 GPIO75 */ +ALTERNATE(PIN_MASK(8, 0x40), 1, MODULE_UART, 0) /* CR_SOUT2 GPIO86 */ +#endif + +/* ADC */ +ALTERNATE(PIN_MASK(4, 0x3E), 1, MODULE_ADC, 0) /* ADC0/1/2/3/4 GPIO45/44/43/42/41 */ +ALTERNATE(PIN_MASK(3, 0x90), 1, MODULE_ADC, 0) /* ADC5/6 GPIO37/34 */ +ALTERNATE(PIN_MASK(E, 0x03), 1, MODULE_ADC, 0) /* ADC7/10 GPIOE1/E0 */ +ALTERNATE(PIN_MASK(F, 0x03), 1, MODULE_ADC, 0) /* ADC8/9 GPIOF1/F0 */ +ALTERNATE(PIN_MASK(C, 0x80), 1, MODULE_ADC, 0) /* ADC11 GPIOC7 */ + +/* SPI */ +ALTERNATE(PIN_MASK(A, 0x0A), 1, MODULE_SPI, 0) /* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */ +ALTERNATE(PIN_MASK(9, 0x20), 1, MODULE_SPI, 0) /* SPIP_MISO GPIO95 */ + +/* PWM */ +ALTERNATE(PIN_MASK(C, 0x10), 1, MODULE_PWM, 0) /* PWM2 for KBLIGHT Test - GPIOC4 */ + +/* Fan (Tachometer) */ +#ifdef CONFIG_FANS +ALTERNATE(PIN_MASK(C, 0x08), 1, MODULE_PWM, 0) /* PWM0 for FAN Test - GPIOC3 */ +#if NPCX_TACH_SEL2 +ALTERNATE(PIN_MASK(9, 0x08), 1, MODULE_PWM, 0) /* TA1_SL1 for FAN Test - GPIO93 */ +#else +ALTERNATE(PIN_MASK(4, 0x01), 1, MODULE_PWM, 0) /* TA1_SL2 for FAN Test - GPIO40 */ +#endif +#endif + +/* I2C Ports */ +ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0) /* I2C0SDA0/SCL0 GPIOB4/B5 */ +ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0) /* I2C1SDA0 GPIO87 */ +ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0) /* I2C1SCL0/I2C2SDA0/SCL0 GPIO90/91/92 */ +ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0) /* I2C3SDA0/SCL0 GPIOD0/D1 */ +ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0) /* I2C7SDA0/SCL0 GPIOB2/B3 */ + +/* Keyboard Columns */ +ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, 0) +ALTERNATE(PIN_MASK(1, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0) +ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, 0) + +/* Keyboard Rows */ +ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, 0) +ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, 0) + +/* PSL for hibernating */ +#ifdef CONFIG_HIBERNATE_PSL +ALTERNATE(PIN_MASK(D, 0x04), 1, MODULE_PMU, 0) /* PSL_IN1 GPIOD2 */ +ALTERNATE(PIN_MASK(0, 0x03), 1, MODULE_PMU, 0) /* PSL_IN2/3/4 GPIO00/01/02 */ +#endif |