summaryrefslogtreecommitdiff
path: root/board/poppy/gpio.inc
diff options
context:
space:
mode:
authorArchana Patni <archana.patni@intel.com>2017-02-23 10:40:47 +0530
committerchrome-bot <chrome-bot@chromium.org>2017-04-03 01:59:15 -0700
commitdf0c0b2b33df8a3594ec7c6503f9577d8bc578c4 (patch)
tree31e6d2a6253573aaf53765b823f4668946851810 /board/poppy/gpio.inc
parent8b04251d50de0059e377a8e2e14360d1cf56a5e6 (diff)
downloadchrome-ec-stabilize-9428.B.tar.gz
Poppy: Enter/exit from S0ix based on host commands from kernelstabilize-9428.B
This patch enables the entry/exit model for S0ix based on host commands. The kernel will send host events on kernel freeze/thaw exit; EC will initiate the S0ix entry based on host command and exit via another host command from kernel. BRANCH=none BUG=b:36630881 TEST=Build/flash EC and check 'echo freeze > /sys/power/state' command in OS shell. Verify EC goes to S0ix state, and on wake it comes back to S0 state. Change-Id: I22405021aead8488a5a1f166400cbde76faac59b Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Archana Patni <archana.patni@intel.com> Reviewed-on: https://chromium-review.googlesource.com/446219 Commit-Ready: Archana Patni <archana.patni@intel.corp-partner.google.com> Tested-by: Archana Patni <archana.patni@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'board/poppy/gpio.inc')
-rw-r--r--board/poppy/gpio.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/poppy/gpio.inc b/board/poppy/gpio.inc
index 673a3a66af..1e5034edd3 100644
--- a/board/poppy/gpio.inc
+++ b/board/poppy/gpio.inc
@@ -10,7 +10,6 @@
GPIO_INT(USB_C0_PD_INT_ODL, PIN(3, 7), GPIO_INT_FALLING, tcpc_alert_event)
GPIO_INT(USB_C1_PD_INT_ODL, PIN(C, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(PCH_SLP_S0_L, PIN(7, 5), GPIO_INT_BOTH, power_signal_interrupt)
/* Use VW signals instead of GPIOs */
#ifndef CONFIG_ESPI_VW_SIGNALS
GPIO_INT(PCH_SLP_S3_L, PIN(7, 3), GPIO_INT_BOTH, power_signal_interrupt)
@@ -50,6 +49,7 @@ GPIO(CCD_MODE_ODL, PIN(6, 3), GPIO_INPUT) /* Case Closed Debug Mode */
GPIO(EC_HAVEN_RESET_ODL, PIN(0, 2), GPIO_ODR_HIGH) /* H1 Reset */
GPIO(ENTERING_RW, PIN(7, 6), GPIO_OUTPUT) /* EC Entering RW */
GPIO(PMIC_INT_L, PIN(6, 0), GPIO_INPUT) /* PMIC interrupt */
+GPIO(PCH_SLP_S0_L, PIN(7, 5), GPIO_INPUT)
/* Sensor interrupts, not implemented yet */
GPIO(ALS_INT_L, PIN(2, 5), GPIO_INPUT)