ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

6 files changed, 0 insertions, 691 deletions

diff --git a/board/quiche/board.c b/board/quiche/board.c
deleted file mode 100644
index e49b2e1b1a..0000000000
--- a/board/quiche/board.c
+++ /dev/null
@@ -1,419 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Quiche board-specific configuration */
-
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/stm32gx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/ps8822.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "usb_descriptor.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "usb_pd_dp_ufp.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_tc_sm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-#define QUICHE_PD_DEBUG_LVL 1
-
-#ifdef SECTION_IS_RW
-#define CROS_EC_SECTION "RW"
-#else
-#define CROS_EC_SECTION "RO"
-#endif
-
-#ifdef SECTION_IS_RW
-static int pd_dual_role_init[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	PD_DRP_TOGGLE_ON,
-	PD_DRP_FORCE_SOURCE,
-};
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_HOST_USBC_PPC_INT_ODL:
-		sn5s330_interrupt(USB_PD_PORT_HOST);
-		break;
-	case GPIO_USBC_DP_PPC_INT_ODL:
-		sn5s330_interrupt(USB_PD_PORT_DP);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal s)
-{
-	int port = -1;
-
-	switch (s) {
-	case GPIO_USBC_DP_MUX_ALERT_ODL:
-		port = USB_PD_PORT_DP;
-		break;
-	default:
-		return;
-	}
-	schedule_deferred_pd_interrupt(port);
-}
-
-void hpd_interrupt(enum gpio_signal signal)
-{
-	usb_pd_hpd_edge_event(signal);
-}
-
-static void board_uf_manage_vbus_interrupt(enum gpio_signal signal)
-{
-	baseboard_usb3_check_state();
-}
-
-static void board_pwr_btn_interrupt(enum gpio_signal signal)
-{
-	baseboard_power_button_evt(gpio_get_level(signal));
-}
-
-static void board_usbc_usb3_interrupt(enum gpio_signal signal)
-{
-	baseboard_usbc_usb3_irq();
-}
-#endif /* SECTION_IS_RW */
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/*
- * Table GPIO signals control both power rails and reset lines to various chips
- * on the board. The order the signals are changed and the delay between GPIO
- * signals is driven by USB/MST hub power sequencing requirements.
- */
-const struct power_seq board_power_seq[] = {
-	{GPIO_EN_AC_JACK,               1, 20},
-	{GPIO_EC_DFU_MUX_CTRL,          0, 0},
-	{GPIO_EN_PP5000_A,              1, 31},
-	{GPIO_MST_LP_CTL_L,             1, 0},
-	{GPIO_EN_PP3300_B,              1, 1},
-	{GPIO_EN_PP1100_A,              1, 100+30},
-	{GPIO_EN_BB,                    1, 30},
-	{GPIO_EN_PP1050_A,              1, 30},
-	{GPIO_EN_PP1200_A,              1, 20},
-	{GPIO_EN_PP5000_C,              1, 20},
-	{GPIO_EN_PP5000_HSPORT,         1, 31},
-	{GPIO_EN_DP_SINK,               1, 80},
-	{GPIO_MST_RST_L,                1, 61},
-	{GPIO_EC_HUB2_RESET_L,          1, 41},
-	{GPIO_EC_HUB3_RESET_L,          1, 33},
-	{GPIO_DP_SINK_RESET,            1, 100},
-	{GPIO_USBC_DP_PD_RST_L,         1, 100},
-	{GPIO_USBC_UF_RESET_L,          1, 33},
-	{GPIO_DEMUX_DUAL_DP_PD_N,       1, 100},
-	{GPIO_DEMUX_DUAL_DP_RESET_N,    1, 100},
-	{GPIO_DEMUX_DP_HDMI_PD_N,       1, 10},
-	{GPIO_DEMUX_DUAL_DP_MODE,       1, 10},
-	{GPIO_DEMUX_DP_HDMI_MODE,       1, 5},
-};
-const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
-
-/*
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Quiche"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      =
-			USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-#ifndef SECTION_IS_RW
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USB_PD_PORT_HOST] = {
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-	},
-};
-#endif
-
-#ifdef SECTION_IS_RW
-/*
- * PS8802 set mux board tuning.
- * Adds in board specific gain and DP lane count configuration
- */
-static int board_ps8822_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-
-	/* DP specific config */
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		rv = ps8822_set_dp_rx_eq(me, PS8822_DPEQ_LEVEL_UP_20DB);
-
-	return rv;
-}
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &stm32gx_tcpm_drv,
-	},
-	[USB_PD_PORT_DP] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_I2C1,
-			.addr_flags = PS8751_I2C_ADDR2_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.usb_port = USB_PD_PORT_HOST,
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = PS8822_I2C_ADDR3_FLAG,
-		.driver = &ps8822_usb_mux_driver,
-		.board_set = &board_ps8822_mux_set,
-	},
-	[USB_PD_PORT_DP] = {
-		.usb_port = USB_PD_PORT_DP,
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = PS8751_I2C_ADDR2_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_DP] = {
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = SN5S330_ADDR2_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_USB3] = {
-		.i2c_port = I2C_PORT_I2C3,
-		.i2c_addr_flags = SN5S330_ADDR1_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-const struct hpd_to_pd_config_t hpd_config = {
-	.port = USB_PD_PORT_HOST,
-	.signal = GPIO_DDI_MST_IN_HPD,
-};
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_SYSTEM, "Resetting TCPCs...");
-	cflush();
-	gpio_set_level(GPIO_USBC_DP_PD_RST_L, 0);
-	gpio_set_level(GPIO_USBC_UF_RESET_L, 0);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-	gpio_set_level(GPIO_USBC_DP_PD_RST_L, 1);
-	gpio_set_level(GPIO_USBC_UF_RESET_L, 1);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-}
-
-void board_enable_usbc_interrupts(void)
-{
-	/* Enable C0 PPC interrupt */
-	gpio_enable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
-	/* Enable C1 PPC interrupt */
-	gpio_enable_interrupt(GPIO_USBC_DP_PPC_INT_ODL);
-	/* Enable C0 HPD interrupt */
-	gpio_enable_interrupt(GPIO_DDI_MST_IN_HPD);
-	/* Enable C1 TCPC interrupt */
-	gpio_enable_interrupt(GPIO_USBC_DP_MUX_ALERT_ODL);
-}
-
-void board_disable_usbc_interrupts(void)
-{
-	/* Disable C0 PPC interrupt */
-	gpio_disable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
-	/* Disable C1 PPC interrupt */
-	gpio_disable_interrupt(GPIO_USBC_DP_PPC_INT_ODL);
-	/* Disable C0 HPD interrupt */
-	gpio_disable_interrupt(GPIO_DDI_MST_IN_HPD);
-	/* Disable C1 TCPC interrupt */
-	gpio_disable_interrupt(GPIO_USBC_DP_MUX_ALERT_ODL);
-	/* Disable VBUS control interrupt for C2 */
-	gpio_disable_interrupt(GPIO_USBC_UF_MUX_VBUS_EN);
-}
-
-void board_tcpc_init(void)
-{
-	board_reset_pd_mcu();
-
-	/* Enable board usbc interrupts */
-	board_enable_usbc_interrupts();
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
-
-enum pd_dual_role_states board_tc_get_initial_drp_mode(int port)
-{
-	return pd_dual_role_init[port];
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	/*
-	 * CONFIG_USB_PD_PORT_MAX_COUNT must be defined to account for C0, C1,
-	 * and C2, but TCPMv2 only knows about C0 and C1, as C2 is a type-c only
-	 * port that is managed directly by the PS8803 TCPC.
-	 */
-	return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USB_PD_PORT_HOST)
-		return gpio_get_level(GPIO_HOST_USBC_PPC_INT_ODL) == 0;
-	else if (port == USB_PD_PORT_DP)
-		return gpio_get_level(GPIO_USBC_DP_PPC_INT_ODL) == 0;
-
-	return 0;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USBC_DP_MUX_ALERT_ODL) &&
-	    gpio_get_level(GPIO_USBC_DP_PD_RST_L))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-static void board_usb_pd_dp_ocp_reset(void)
-{
-	gpio_set_level(GPIO_USBC_ALTMODE_OCP_NOTIFY, 1);
-}
-DECLARE_DEFERRED(board_usb_pd_dp_ocp_reset);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	if (port == USB_PD_PORT_DP) {
-		gpio_set_level(GPIO_USBC_ALTMODE_OCP_NOTIFY, !is_overcurrented);
-		hook_call_deferred(&board_usb_pd_dp_ocp_reset_data,
-				   USB_HUB_OCP_RESET_MSEC);
-	}
-}
-
-int dock_get_mf_preference(void)
-{
-	int rv;
-	uint32_t fw_config;
-	int mf = MF_OFF;
-
-	/*
-	 * MF (multi function) preferece is indicated by bit 0 of the fw_config
-	 * data field. If this data field does not exist, then default to 4 lane
-	 * mode.
-	 */
-	rv = cbi_get_fw_config(&fw_config);
-	if (!rv)
-		mf = CBI_FW_MF_PREFERENCE(fw_config);
-
-	return mf;
-}
-
-#endif /* SECTION_IS_RW */
-
-static void board_init(void)
-{
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_debug_gpio_1_pulse(void)
-{
-	gpio_set_level(GPIO_TRIGGER_1, 0);
-}
-DECLARE_DEFERRED(board_debug_gpio_1_pulse);
-
-static void board_debug_gpio_2_pulse(void)
-{
-	gpio_set_level(GPIO_TRIGGER_2, 0);
-}
-DECLARE_DEFERRED(board_debug_gpio_2_pulse);
-
-void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec)
-{
-	switch (trigger) {
-	case TRIGGER_1:
-		gpio_set_level(GPIO_TRIGGER_1, level);
-		if (pulse_usec)
-			hook_call_deferred(&board_debug_gpio_1_pulse_data,
-					   pulse_usec);
-		break;
-	case TRIGGER_2:
-		gpio_set_level(GPIO_TRIGGER_2, level);
-		if (pulse_usec)
-			hook_call_deferred(&board_debug_gpio_2_pulse_data,
-					   pulse_usec);
-		break;
-	default:
-		CPRINTS("bad debug gpio selection");
-		break;
-	}
-}
-
-static int command_dplane(int argc, char **argv)
-{
-	char *e;
-	int lane;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	lane = strtoi(argv[1], &e, 10);
-
-	if ((lane != 2) && (lane != 4))
-		return EC_ERROR_PARAM1;
-
-	/* put MST into reset */
-	gpio_set_level(GPIO_MST_RST_L, 0);
-	msleep(1);
-	/* Set lane control to requested level */
-	gpio_set_level(GPIO_MST_HUB_LANE_SWITCH, lane == 2 ? 1 : 0);
-	msleep(1);
-	/* Take MST out of reset */
-	gpio_set_level(GPIO_MST_RST_L, 1);
-
-	ccprintf("MST lane set:  %s, lane_ctrl = %d\n",
-		 lane == 2 ? "2 lane" : "4 lane",
-		 gpio_get_level(GPIO_MST_HUB_LANE_SWITCH));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dplane, command_dplane,
-			"<2 | 4>",
-			"MST lane control.");
diff --git a/board/quiche/board.h b/board/quiche/board.h
deleted file mode 100644
index 98feab31f6..0000000000
--- a/board/quiche/board.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Quiche board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-/*
- * For MP release, CONFIG_SYSTEM_UNLOCKED must be undefined, and
- * CONFIG_FLASH_PSTATE_LOCKED must be defined in order to enable write protect
- * using option bytes WRP registers.
- */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-#undef CONFIG_FLASH_PSTATE_LOCKED
-
-
-/* USB Type C and USB PD defines */
-#define USB_PD_PORT_HOST   0
-#define USB_PD_PORT_DP     1
-#define USB_PD_PORT_USB3   2
-
-/*
- * The host (C0) and display (C1) usbc ports are usb-pd capable. There is
- * also a type-c only port (C2). C2 must be accounted for in PORT_MAX_COUNT so
- * the PPC config table is correctly sized and the PPC driver can be used to
- * control VBUS on/off.
- */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 3
-#define CONFIG_USB_MUX_PS8822
-
-#define CONFIG_USB_PID 0x5048
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
-#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
-#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
-
-/* I2C port names */
-#define I2C_PORT_I2C1	0
-#define I2C_PORT_I2C2	1
-#define I2C_PORT_I2C3	2
-
-/* Required symbolic I2C port names */
-#define I2C_PORT_MP4245 I2C_PORT_I2C3
-#define I2C_PORT_EEPROM I2C_PORT_I2C3
-#define MP4245_I2C_ADDR_FLAGS MP4245_I2C_ADDR_0_FLAGS
-
-/* Include math_util for bitmask_uint64 used in pd_timers */
-#define CONFIG_MATH_UTIL
-
-#ifndef __ASSEMBLER__
-
-#include "registers.h"
-
-#define GPIO_DP_HPD GPIO_DDI_MST_IN_HPD
-#define GPIO_USBC_UF_ATTACHED_SRC GPIO_USBC_UF_MUX_VBUS_EN
-#define GPIO_BPWR_DET GPIO_TP73
-#define GPIO_USB_HUB_OCP_NOTIFY GPIO_USBC_DATA_OCP_NOTIFY
-#define GPIO_UFP_PLUG_DET GPIO_MST_UFP_PLUG_DET
-#define GPIO_PWR_BUTTON_RED GPIO_EC_STATUS_LED1
-#define GPIO_PWR_BUTTON_GREEN GPIO_EC_STATUS_LED2
-
-#define BUTTON_PRESSED_LEVEL 1
-#define BUTTON_RELEASED_LEVEL 0
-
-#define GPIO_TRIGGER_1 GPIO_EC_STATUS_LED1
-#define GPIO_TRIGGER_2 GPIO_EC_STATUS_LED2
-
-enum  debug_gpio {
-	TRIGGER_1 = 0,
-	TRIGGER_2,
-};
-
-/*
- * Function used to control GPIO signals as a timing marker. This is intended to
- * be used for development/debugging purposes.
- *
- * @param trigger GPIO debug signal selection
- * @param level desired level of the debug gpio signal
- * @param pulse_usec pulse width if non-zero
- */
-void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec);
-
-/*
- * Function called in power on case to enable usbc related interrupts
- */
-void board_enable_usbc_interrupts(void);
-
-/*
- * Function called in power off case to disable usbc related interrupts
- */
-void board_disable_usbc_interrupts(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/quiche/build.mk b/board/quiche/build.mk
deleted file mode 100644
index 1a8ec0d625..0000000000
--- a/board/quiche/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=stm32
-CHIP_FAMILY:=stm32g4
-CHIP_VARIANT:=stm32g473xc
-BASEBOARD:=honeybuns
-
-board-y=board.o
diff --git a/board/quiche/dev_key.pem b/board/quiche/dev_key.pem
deleted file mode 100644
index 4897ceb44e..0000000000
--- a/board/quiche/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4wIBAAKCAYEAyiT9PsD2wW3mhfuxMtihnLDKC+PY9l6j+j405G5Wd3BBtLLl
-2uEoSD8cFQfnVTeFH7wggVf+SMAP3Y2aTnXIfdTX3N0skAdq/kYNUlQAK0xsa3Z7
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-oDE2QlXXmd1higPaQe3u+7vmh6itVpJ71n9wmu9xei7IiTOtGDYjHLXa8Qg0y37/
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-QnC0WfVF9amWNGwocKATkwjoSVC7rQRsB2FMbY/WCqgE92lXsU9W
------END RSA PRIVATE KEY-----
diff --git a/board/quiche/ec.tasklist b/board/quiche/ec.tasklist
deleted file mode 100644
index cc36bf5a74..0000000000
--- a/board/quiche/ec.tasklist
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(POWER_BUTTON, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(PD_INT_C1, pd_interrupt_handler_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(UCPD, ucpd_task, 0, LARGER_TASK_STACK_SIZE)
diff --git a/board/quiche/gpio.inc b/board/quiche/gpio.inc
deleted file mode 100644
index 9514858ca7..0000000000
--- a/board/quiche/gpio.inc
+++ /dev/null
@@ -1,100 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-#ifdef SECTION_IS_RW
-GPIO_INT(HOST_USBC_PPC_INT_ODL,  PIN(D,  9),      GPIO_INT_FALLING | GPIO_PULL_UP, ppc_interrupt)
-GPIO_INT(USBC_DP_MUX_ALERT_ODL,  PIN(B,  1),      GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)
-GPIO_INT(USBC_DP_PPC_INT_ODL,    PIN(E,  7),      GPIO_INT_FALLING | GPIO_PULL_UP, ppc_interrupt)
-GPIO_INT(DDI_MST_IN_HPD,         PIN(C,  14),     GPIO_INT_BOTH, hpd_interrupt)
-GPIO_INT(USBC_UF_MUX_VBUS_EN,    PIN(C,  12),     GPIO_INT_BOTH, board_uf_manage_vbus_interrupt)
-GPIO_INT(PWR_BTN,                PIN(A,  0),      GPIO_INT_BOTH, board_pwr_btn_interrupt)
-GPIO_INT(USBC_UF_PPC_INT_ODL,    PIN(B,  5),      GPIO_INT_FALLING | GPIO_PULL_UP, board_usbc_usb3_interrupt)
-#endif
-
-/* Power sequencing signals */
-GPIO(EN_AC_JACK,                    PIN(A,  1), GPIO_OUT_LOW)
-GPIO(EN_BB,                         PIN(A,  8), GPIO_OUT_LOW)
-GPIO(EN_PP3300_B,                   PIN(B,  2), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,                   PIN(C,  6), GPIO_OUT_LOW)
-GPIO(EN_PP1200_A,                   PIN(E,  8), GPIO_OUT_LOW)
-GPIO(EN_PP1100_A,                   PIN(C,  7), GPIO_OUT_LOW)
-GPIO(EN_PP1050_A,                   PIN(A,  2), GPIO_OUT_LOW)
-GPIO(EN_PP5000_C,                   PIN(D,  1), GPIO_OUT_LOW)
-GPIO(EN_PP5000_HSPORT,              PIN(D,  0), GPIO_OUT_LOW)
-
-/* MST Hub signals */
-GPIO(MST_LP_CTL_L,                  PIN(D, 10), GPIO_ODR_LOW)
-GPIO(MST_RST_L,                     PIN(E, 14), GPIO_ODR_LOW)
-GPIO(MST_HUB_LANE_SWITCH,           PIN(C, 15), GPIO_OUT_HIGH)
-GPIO(MST_UFP_PLUG_DET,              PIN(B, 12), GPIO_OUT_HIGH)
-
-/* Display Demux signals */
-GPIO(DEMUX_DUAL_DP_MODE,            PIN(B,  0), GPIO_OUT_LOW)
-GPIO(DEMUX_DP_HDMI_MODE,            PIN(E, 15), GPIO_OUT_LOW)
-GPIO(DEMUX_DUAL_DP_RESET_N,         PIN(E, 13), GPIO_ODR_LOW)
-GPIO(DEMUX_DUAL_DP_PD_N,            PIN(E, 12), GPIO_ODR_LOW)
-GPIO(DEMUX_DP_HDMI_PD_N,            PIN(B, 13), GPIO_ODR_LOW)
-
-/* USBC Mux and Demux Signals */
-GPIO(EN_DP_SINK,                    PIN(B, 14), GPIO_OUT_LOW)
-GPIO(DP_SINK_RESET,                 PIN(B, 15), GPIO_OUT_LOW)
-GPIO(USBC_DP_PD_RST_L,              PIN(E,  9), GPIO_ODR_LOW)
-GPIO(USBC_UF_RESET_L,               PIN(D,  2), GPIO_ODR_LOW)
-
-/* USB Hubs signals */
-GPIO(EC_HUB2_RESET_L,               PIN(C,  5), GPIO_ODR_LOW)
-GPIO(EC_HUB3_RESET_L,               PIN(B, 10), GPIO_ODR_LOW)
-GPIO(USBC_ALTMODE_OCP_NOTIFY,       PIN(F,  0), GPIO_OUT_HIGH)
-GPIO(USBC_DATA_OCP_NOTIFY,          PIN(F,  1), GPIO_OUT_HIGH)
-
-/* USB-A Current limit switches, set default to 1.5A */
-GPIO(TP73,                          PIN(C,  0), GPIO_OUT_LOW)
-GPIO(EC_DFU_MUX_CTRL,               PIN(C,  3), GPIO_OUT_HIGH)
-GPIO(EC_STATUS_LED1,                PIN(C,  1), GPIO_OUT_HIGH)
-GPIO(EC_STATUS_LED2,                PIN(C,  2), GPIO_OUT_HIGH)
-GPIO(USB3_A5_CDP_EN,                PIN(B,  9), GPIO_OUT_LOW)
-GPIO(USB3_A6_CDP_EN,                PIN(C, 13), GPIO_OUT_LOW)
-
-/* Write protect */
-GPIO(EC_FLASH_WP_ODL,               PIN(A,  3), GPIO_ODR_HIGH)
-GPIO(EC_WP_L,                       PIN(E, 11), GPIO_INT_BOTH)
-
-/* UART Bus */
-GPIO(EC_UART_TX,                    PIN(C, 10), GPIO_INT_BOTH)
-GPIO(EC_UART_RX,                    PIN(C, 11), GPIO_INT_BOTH)
-
-/*
- * I2C SCL/SDA pins. These will normally be under control of the peripheral from
- * alt fucntion setting below. But if a port gets wedged, the unwedge code uses
- * these signals as regular GPIOs.
- */
-GPIO(EC_I2C1_SCL,                   PIN(A, 15),  GPIO_ODR_HIGH)
-GPIO(EC_I2C1_SDA,                   PIN(B,  7),  GPIO_ODR_HIGH)
-GPIO(EC_I2C3_SCL,                   PIN(C,  8),  GPIO_ODR_HIGH)
-GPIO(EC_I2C3_SDA,                   PIN(C,  9),  GPIO_ODR_HIGH)
-
-/* misc signals */
-GPIO(BOOT0,                         PIN(B,  8),  GPIO_INPUT)
-
-/* Unimplemented signals since we are not an EC */
-UNIMPLEMENTED(ENTERING_RW)
-
-/* USART3_TX/RX GPIOC 10-11*/
-ALTERNATE(PIN_MASK(C, 0x0C00),  7, MODULE_UART,  GPIO_PULL_UP)
-/* I2C Ports
- *   I2C1: SDA/SCL -> PB7/PA15
- *   I2C2: SDA/SCL -> PA8/PA9
- *   I2C3: SDA/SCL -> PC8/PC9
- */
-ALTERNATE(PIN_MASK(B, 0x0080),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
-ALTERNATE(PIN_MASK(A, 0X8000),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
-ALTERNATE(PIN_MASK(C, 0x0300),  8, MODULE_I2C,   GPIO_OPEN_DRAIN)
-/* GPIOA4-7: SPI Signals */
-ALTERNATE(PIN_MASK(A, 0x00F0),  5, MODULE_SPI,   0)