diff options
author | li feng <li1.feng@intel.com> | 2016-06-22 17:25:01 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2016-06-27 17:14:01 -0700 |
commit | 66b2f33e7dc929e64298f71707ce2f912b592129 (patch) | |
tree | 0e6c681088af9cd06e8e32e4a8b1dc04e8ee70e2 /board/reef/gpio.inc | |
parent | e84a71fe67c08dd3d1777c0cd22fd1e35ea1d7e0 (diff) | |
download | chrome-ec-66b2f33e7dc929e64298f71707ce2f912b592129.tar.gz |
reef: Support DP alt mode of Type-C controller
BUG=chrome-os-partner:54413,chrome-os-partner:54649
BRANCH=none
TEST=none
Change-Id: I32c969a97f84bf4e9953031c69008f8e598b7920
Signed-off-by: li feng <li1.feng@intel.com>
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/355604
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'board/reef/gpio.inc')
-rw-r--r-- | board/reef/gpio.inc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc index 853aea32a7..755b3f75d7 100644 --- a/board/reef/gpio.inc +++ b/board/reef/gpio.inc @@ -12,7 +12,7 @@ GPIO_INT(CHARGER_INT_L, PIN(3, 3), GPIO_INT_FALLING, bd99955_vbus_interrupt) / GPIO_INT(USB_C0_PD_INT, PIN(3, 7), GPIO_INT_RISING, tcpc_alert_event) /* from Analogix TCPC */ GPIO_INT(USB_C1_PD_INT_ODL, PIN(D, 2), GPIO_INT_FALLING, tcpc_alert_event) /* from Parade TCPC */ -GPIO_INT(PCH_SLP_S4_L, PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4_L */ +GPIO_INT(PCH_SLP_S4_L, PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4_L */ GPIO_INT(PCH_SLP_S3_L, PIN(7, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S3_L */ GPIO_INT(PCH_SLP_S0_L, PIN(7, 5), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */ GPIO_INT(SUSPWRNACK, PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt) @@ -82,7 +82,7 @@ GPIO(USB_C0_CABLE_DET, PIN(C, 5), GPIO_INPUT) GPIO(PCH_RSMRST_L, PIN(7, 0), GPIO_OUT_LOW) GPIO(EC_BATT_PRES_L, PIN(3, 4), GPIO_INPUT) GPIO(V5A_EN, PIN(8, 5), GPIO_OUT_LOW) /* PMIC_EN */ -GPIO(EN_PP3300, PIN(C, 2), GPIO_OUT_LOW) +GPIO(EN_PP3300, PIN(C, 2), GPIO_OUT_LOW) GPIO(PP3300_PG, PIN(6, 2), GPIO_INPUT) GPIO(EN_PP5000, PIN(C, 6), GPIO_OUT_LOW) GPIO(PP5000_PG, PIN(7, 1), GPIO_INPUT) @@ -92,13 +92,13 @@ GPIO(ENABLE_BACKLIGHT, PIN(9, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_BL_EN_OD GPIO(WIRELESS_GPIO_WLAN_POWER, PIN(6, 6), GPIO_ODR_HIGH) /* EN_PP3300_WLAN_ODL */ -GPIO(CPU_PROCHOT, PIN(7, 4), GPIO_INPUT | GPIO_SEL_1P8V) /* PCH_PROCHOT_ODL */ +GPIO(CPU_PROCHOT, PIN(7, 4), GPIO_INPUT | GPIO_SEL_1P8V) /* PCH_PROCHOT_ODL */ GPIO(EC_PCH_PROCHOT_OVERRIDE_ODL,PIN(A, 3), GPIO_ODR_HIGH | GPIO_SEL_1P8V) GPIO(PCH_PWRBTN_L, PIN(0, 1), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */ GPIO(PCH_WAKE_L, PIN(8, 1), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ -GPIO(USB_C0_HPD_1P8_ODL, PIN(9, 4), GPIO_ODR_HIGH) -GPIO(USB_C1_HPD_1P8_ODL, PIN(A, 5), GPIO_ODR_HIGH) +GPIO(USB_C0_HPD_1P8_ODL, PIN(9, 4), GPIO_INPUT | GPIO_SEL_1P8V) +GPIO(USB_C1_HPD_1P8_ODL, PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V) GPIO(USB2_OTG_ID, PIN(A, 1), GPIO_OUTPUT) /* FIXME: what should this init to? */ GPIO(USB2_OTG_VBUSSENSE, PIN(9, 5), GPIO_OUTPUT) |