diff options
| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2019-05-30 16:25:15 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-06-13 23:02:44 +0000 |
| commit | 8ca44cb4eca69d44e9fce0b93b58be9c7d9d19f3 (patch) | |
| tree | 4913ea0403d24fc4574bfa2941ee4de7e28a000c /board/reef_it8320/gpio.inc | |
| parent | 037eb91f65510d2949289f837c716b7fa997746f (diff) | |
| download | chrome-ec-8ca44cb4eca69d44e9fce0b93b58be9c7d9d19f3.tar.gz | |
intel_x86/power: Consolidate chipset specific power signals array
Currently chipset specific power signals are defined at board/baseboard
level. These power signals are moved to chipset specific file to minimize
the redundant power signals array defined for each board/baseboard.
BUG=b:134079574
BRANCH=none
TEST=make buildall -j
Change-Id: I351904f7cd2e0f27844c0711beb118d390219581
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'board/reef_it8320/gpio.inc')
| -rw-r--r-- | board/reef_it8320/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/reef_it8320/gpio.inc b/board/reef_it8320/gpio.inc index 6c07d19f38..808787d475 100644 --- a/board/reef_it8320/gpio.inc +++ b/board/reef_it8320/gpio.inc @@ -18,7 +18,7 @@ GPIO_INT(EC_VOLDN_BTN_ODL, PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_inter #ifdef CONFIG_POWER_S0IX GPIO_INT(PCH_SLP_S0_L, PIN(B, 7), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */ #endif -GPIO_INT(SUSPWRNACK, PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt) /* SUSPWRNACK */ +GPIO_INT(SUSPWRDNACK, PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt) /* SUSPWRNACK */ GPIO_INT(LID_OPEN, PIN(E, 2), GPIO_INT_BOTH, lid_interrupt) /* LID_OPEN */ #ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS GPIO_INT(PCH_PLTRST_L, PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP, lpcrst_interrupt) /* PLT_RST_L */ |