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| author | Leifu Zhao <leifu.zhao@intel.com> | 2020-02-14 10:57:59 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-02-27 00:29:05 +0000 |
| commit | 3e8d6447b38d8083ef6e6c6321e0e5b8b9f9c38f (patch) | |
| tree | 1f0b4ce2ad3691f380f6003b2c12c5dcedbbc256 /board/tglrvp_ish | |
| parent | 3f1dc59f201a5e3f52c1f0b6e72c8a166ea8dacf (diff) | |
| download | chrome-ec-3e8d6447b38d8083ef6e6c6321e0e5b8b9f9c38f.tar.gz | |
ish: board level PM enablement for tgl rvp
Board level power management enablement for tgl rvp.
BUG=b:149238813
BRANCH=none
TEST=ISH can successfully enter into D0i1/D0i2/D0i3 on tgl rvp.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: Ie1eaa532a38a286ca47540cb41edc8044cd7352b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2056150
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Diffstat (limited to 'board/tglrvp_ish')
| -rw-r--r-- | board/tglrvp_ish/board.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/board/tglrvp_ish/board.h b/board/tglrvp_ish/board.h index cadd6cf8fe..07de274bdd 100644 --- a/board/tglrvp_ish/board.h +++ b/board/tglrvp_ish/board.h @@ -67,6 +67,23 @@ #undef CONFIG_ADC #undef CONFIG_SHA256 +/* DMA paging between SRAM and DRAM */ +#define CONFIG_DMA_PAGING + +/* power management definitions */ +#define CONFIG_LOW_POWER_IDLE + +#define CONFIG_ISH_PM_D0I1 +#define CONFIG_ISH_PM_D0I2 +#define CONFIG_ISH_PM_D0I3 +#define CONFIG_ISH_PM_D3 +#define CONFIG_ISH_PM_RESET_PREP + +#define CONFIG_ISH_D0I2_MIN_USEC (15*MSEC) +#define CONFIG_ISH_D0I3_MIN_USEC (50*MSEC) + +#define CONFIG_ISH_NEW_PM + #ifndef __ASSEMBLER__ #include "gpio_signal.h" |