diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2021-11-04 12:11:58 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-05 04:22:34 +0000 |
| commit | 252457d4b21f46889eebad61d4c0a65331919cec (patch) | |
| tree | 01856c4d31d710b20e85a74c8d7b5836e35c3b98 /board/vilboz/gpio.inc | |
| parent | 08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff) | |
| download | chrome-ec-stabilize-14588.98.B-ish.tar.gz | |
ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'board/vilboz/gpio.inc')
| -rw-r--r-- | board/vilboz/gpio.inc | 126 |
1 files changed, 0 insertions, 126 deletions
diff --git a/board/vilboz/gpio.inc b/board/vilboz/gpio.inc deleted file mode 100644 index 78baa0eccc..0000000000 --- a/board/vilboz/gpio.inc +++ /dev/null @@ -1,126 +0,0 @@ -/* -*- mode:c -*- - * - * Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Declare symbolic names for all the GPIOs that we care about. - * Note: Those with interrupt handlers must be declared first. */ - -GPIO_INT(USB_C0_TCPC_INT_ODL, PIN(3, 4), GPIO_INT_FALLING, tcpc_alert_event) -GPIO_INT(USB_C0_PPC_FAULT_ODL, PIN(6, 3), GPIO_INT_FALLING, ppc_interrupt) -GPIO_INT(USB_C0_BC12_INT_ODL, PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP, bc12_interrupt) -GPIO_INT(SLP_S3_L, PIN(7, 4), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(SLP_S5_L, PIN(E, 0), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(S0_PWROK_OD, PIN(5, 6), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(EC_PWROK_OD, PIN(3, 7), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(EC_PWR_BTN_ODL, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt) -GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) -GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt) -GPIO_INT(EC_WP_L, PIN(5, 0), GPIO_INT_BOTH, switch_interrupt) -GPIO_INT(VOLDN_BTN_ODL, PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) -GPIO_INT(VOLUP_BTN_ODL, PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) -GPIO_INT(6AXIS_INT_L, PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP, lsm6dsm_interrupt) -GPIO_INT(HDMI_CONN_HPD_3V3, PIN(D, 4), GPIO_INT_BOTH | GPIO_PULL_UP, hdmi_hpd_interrupt) - -/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */ -GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) - -GPIO(3AXIS_INT_L, PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN) /* 3 Axis Accel */ -GPIO(CCD_MODE_ODL, PIN(C, 6), GPIO_INPUT) /* Case Closed Debug Mode */ -GPIO(PROCHOT_ODL, PIN(D, 5), GPIO_ODR_HIGH) /* PROCHOT to SOC */ -GPIO(EC_BATT_PRES_ODL, PIN(4, 1), GPIO_INPUT) /* Battery Present */ -GPIO(EC_AP_INT_ODL, PIN(A, 3), GPIO_ODR_HIGH) /* Sensor MKBP event to SOC */ -GPIO(EN_PWR_A, PIN(B, 7), GPIO_OUT_LOW) /* Enable Power */ -GPIO(EC_EDP_BL_DISABLE, PIN(A, 2), GPIO_OUT_HIGH) /* Enable Backlight */ -GPIO(EC_ENTERING_RW, PIN(E, 5), GPIO_OUT_LOW) /* EC Entering RW */ -GPIO(EC_FCH_PWR_BTN_L, PIN(6, 7), GPIO_OUT_HIGH) /* Power Button to SOC */ -GPIO(EC_FCH_RSMRST_L, PIN(A, 1), GPIO_OUT_LOW) /* RSMRST# to SOC */ -GPIO(EC_FCH_PWROK, PIN(7, 0), GPIO_OUT_LOW) /* Power OK to SOC */ -GPIO(EC_FCH_WAKE_L, PIN(0, 3), GPIO_OUT_HIGH) /* Wake SOC */ -GPIO(EC_FCH_SCI_ODL, PIN(7, 6), GPIO_ODR_HIGH) /* SCI to SOC */ -GPIO(EC_SYS_RST_L, PIN(C, 7), GPIO_ODR_HIGH) /* Cold Reset to SOC */ -GPIO(USB_C0_TCPC_RST_L, PIN(E, 1), GPIO_OUT_HIGH) /* C0 TCPC Reset */ -GPIO(EN_USB_A1_5V, PIN(F, 0), GPIO_OUT_LOW) /* A1 5V Source Enable */ -GPIO(USB3_C0_DP2_HPD, PIN(F, 5), GPIO_OUT_LOW) /* C0 DP Hotplug Detect */ -GPIO(DP1_HPD, PIN(F, 4), GPIO_OUT_LOW) /* C1 DP Hotplug Detect */ -GPIO(EC_H1_PACKET_MODE, PIN(8, 6), GPIO_OUT_LOW) /* H1 Packet Mode */ - -UNIMPLEMENTED(PCH_SMI_L) - -GPIO(LED_FULL_L, PIN(6, 0), GPIO_OUT_HIGH) -GPIO(LED_CHRG_L, PIN(C, 0), GPIO_OUT_HIGH) -GPIO(LED3_PWM, PIN(C, 3), GPIO_OUT_HIGH) - -/* LTE control */ -GPIO(LTE_EN, PIN(6, 2), GPIO_OUT_LOW) /* WWAN LTE Function enable */ -GPIO(LTE_W_DISABLE_L, PIN(4, 0), GPIO_OUT_LOW) /* WWAN LTE flight mode */ -GPIO(LTE_FCPO, PIN(7, 3), GPIO_OUT_LOW) /* WWAN LTE Full Card Power ON OFF */ - -/* - * Vilboz has only 1 HDMI DB option - */ -IOEX_INT(USB_C0_SBU_FAULT_ODL, EXPIN(IOEX_C0_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt) - -IOEX(USB_C0_FAULT_ODL, EXPIN(IOEX_C0_NCT3807, 0, 3), GPIO_ODR_HIGH) /* C0 Fault to SOC */ -IOEX(USB_C0_TCPC_FASTSW_CTL_EN, EXPIN(IOEX_C0_NCT3807, 0, 4), GPIO_OUT_LOW) /* C0 FastSwitch Control */ -IOEX(USB_C0_PPC_ILIM_3A_EN, EXPIN(IOEX_C0_NCT3807, 1, 1), GPIO_OUT_LOW) /* C0 3A Current Limit Enable */ -IOEX(KB_BL_EN, EXPIN(IOEX_C0_NCT3807, 1, 3), GPIO_OUT_LOW) /* KB Backlight Enable */ -IOEX(EN_USB_A0_5V, EXPIN(IOEX_C0_NCT3807, 1, 5), GPIO_OUT_LOW) /* A0 5V Source Enable */ -UNIMPLEMENTED(USB_A0_CHARGE_EN_L) -IOEX(USB_C0_SBU_FLIP, EXPIN(IOEX_C0_NCT3807, 1, 7), GPIO_OUT_LOW) /* C0 SBU Flip */ -UNIMPLEMENTED(USB_A1_CHARGE_EN_DB_L) - -/* - * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)] - * is not defined here as GPIO. - */ - -/* I2C pins - these will be reconfigured for alternate function below */ -GPIO(EC_I2C_USB_A0_C0_SCL, PIN(B, 5), GPIO_INPUT) -GPIO(EC_I2C_USB_A0_C0_SDA, PIN(B, 4), GPIO_INPUT) -GPIO(EC_I2C_USB_A1_C1_SCL, PIN(9, 0), GPIO_INPUT) -GPIO(EC_I2C_USB_A1_C1_SDA, PIN(8, 7), GPIO_INPUT) -GPIO(EC_I2C_POWER_SCL, PIN(9, 2), GPIO_INPUT) -GPIO(EC_I2C_POWER_SDA, PIN(9, 1), GPIO_INPUT) -GPIO(EC_I2C_USBC_AP_MUX_SCL, PIN(D, 1), GPIO_INPUT) -GPIO(EC_I2C_USBC_AP_MUX_SDA, PIN(D, 0), GPIO_INPUT) -GPIO(FCH_SIC, PIN(F, 3), GPIO_INPUT) -GPIO(FCH_SID, PIN(F, 2), GPIO_INPUT) -GPIO(EC_I2C_SENSOR_CBI_SCL, PIN(3, 3), GPIO_INPUT) -GPIO(EC_I2C_SENSOR_CBI_SDA, PIN(3, 6), GPIO_INPUT) -GPIO(I2C_AUDIO_USB_HUB_SCL, PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V) -GPIO(I2C_AUDIO_USB_HUB_SDA, PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V) -GPIO(EC_I2C_BATT_SCL, PIN(B, 3), GPIO_INPUT) -GPIO(EC_I2C_BATT_SDA, PIN(B, 2), GPIO_INPUT) - -ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */ - -ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0) /* I2C0 */ -ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0) /* I2C1 SCL / I2C2 */ -ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0) /* I2C1 SDA */ -ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0) /* I2C3 */ -ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0) /* I2C4 */ -ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0) /* I2C5 */ -ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0) /* I2C6 */ -ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0) /* I2C7 */ - -ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0) /* ADC2, ADC3 Temp Sensors */ - -ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0) /* PWM3 KB Backlight */ - -ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_00-01 */ -ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_02-07 */ -ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */ -GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW) /* KSO_02 inverted */ -ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */ -ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-12 */ - -/* Power Switch Logic (PSL) inputs */ -ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0) /* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */ -ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0) /* LID_OPEN */ - -ALTERNATE(PIN_MASK(A, 0xA0), 1, MODULE_WOV, 0) /* I2S_SYNC/I2S_SCLK GPIOA5/A7 */ -ALTERNATE(PIN_MASK(B, 0x01), 1, MODULE_WOV, 0) /* I2S_SDAT GPIOB0 */ -ALTERNATE(PIN_MASK(9, 0x90), 1, MODULE_WOV, 0) /* DMIC_CLK/DMIC_IN GPIO94/97 */ |