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| author | Keith Short <keithshort@chromium.org> | 2020-03-04 12:53:25 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-04-09 00:56:31 +0000 |
| commit | 3b831bbf6ee24a09ef65064d7374e6ef7960eedf (patch) | |
| tree | 1e60e398e159b257a3cba56bc037844d0b289d84 /board/volteer/board.h | |
| parent | 4d39614441258dc5788c2a55000abe56ac43d3fe (diff) | |
| download | chrome-ec-3b831bbf6ee24a09ef65064d7374e6ef7960eedf.tar.gz | |
icelake: Cleanup power sequencing for IceLake/TigerLake/JasperLake
Configure PWROK generation related signals for Ice Lake, Tiger Lake, and
Jasper Lake SoCs. The array driven sequencing provides better
flexibility for the PWROK signals, some of which may be automatically
handled by the platform and some require EC control.
BUG=b:150726713
BRANCH=none
TEST=make buildall
TEST=Volteer: verify VCCIN enable and SYS_PWROK generation during S0 and
verify signals are deasserted when exiting S0.
TEST=Wadledoo: verified 2ms delay between ALL_SYS_PWRGD and PCH_PWROK,
verified JPL sequences to S0.
Change-Id: Iceae29c65398643839b31f6cd757352282849fda
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2088285
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'board/volteer/board.h')
| -rw-r--r-- | board/volteer/board.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/board/volteer/board.h b/board/volteer/board.h index 8ebc01ede8..3c7bd930a9 100644 --- a/board/volteer/board.h +++ b/board/volteer/board.h @@ -72,7 +72,6 @@ #define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL #define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL #define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK #define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L #define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L #define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK |