diff options
| author | Keith Short <keithshort@chromium.org> | 2019-09-19 14:28:41 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-09-27 02:46:15 +0000 |
| commit | 7d3b318f8d77f039eb1fa6c7df7f33a7ca77b262 (patch) | |
| tree | 0ebb8d3ad7c4cc7bd149b6182949193e0bdab16f /board/volteer | |
| parent | 344f19b1c150d0a3fc5f88b45735ab5910c16783 (diff) | |
| download | chrome-ec-7d3b318f8d77f039eb1fa6c7df7f33a7ca77b262.tar.gz | |
volteer: Configure the GPIOs connected to the AP/PCH
This change also corrects the SYS_RESET_L signal.
BUG=b:141265267
BRANCH=none
TEST=make buildall
Change-Id: I9661521ccc0296924840e1a0de02439800c9ca15
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816867
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Diffstat (limited to 'board/volteer')
| -rw-r--r-- | board/volteer/board.h | 5 | ||||
| -rw-r--r-- | board/volteer/gpio.inc | 28 |
2 files changed, 27 insertions, 6 deletions
diff --git a/board/volteer/board.h b/board/volteer/board.h index 45511fe989..92fbdb3105 100644 --- a/board/volteer/board.h +++ b/board/volteer/board.h @@ -43,16 +43,17 @@ * which purpose. */ #define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L EC_PCH_INT_ODL #define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW #define GPIO_LID_OPEN GPIO_EC_LID_OPEN #define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL #define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL #define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_EC_RST_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL #define GPIO_WP_L GPIO_EC_WP_L - #ifndef __ASSEMBLER__ #include "gpio_signal.h" diff --git a/board/volteer/gpio.inc b/board/volteer/gpio.inc index fcc74d05db..604431ca98 100644 --- a/board/volteer/gpio.inc +++ b/board/volteer/gpio.inc @@ -24,11 +24,25 @@ GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex /* Volume button interrupts */ -/* AP Signals */ -GPIO(EC_RST_ODL, PIN(0, 2), GPIO_ODR_HIGH) -GPIO(EC_ENTERING_RW, PIN(E, 3), GPIO_OUT_LOW) -GPIO(EC_PCH_WAKE_ODL, PIN(7, 4), GPIO_ODR_HIGH) +/* Other wake sources */ +/* + * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an + * interrupt handler because it is automatically handled by the PSL. + */ +GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) + +/* AP/PCH Signals */ +GPIO(EC_PCH_SYS_PWROK, PIN(3, 7), GPIO_OUT_LOW) /* TODO - b/140556273 - implement support with power sequencing */ +GPIO(EC_PCH_RSMRST_ODL, PIN(A, 6), GPIO_ODR_HIGH) /* TODO - b/140950085 - implement TGL sequencing requirement */ GPIO(EC_PCH_PWR_BTN_ODL, PIN(C, 1), GPIO_ODR_HIGH) +GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* TODO - b/141321096 - implement reset logic for RTC */ +GPIO(EC_PCH_WAKE_ODL, PIN(7, 4), GPIO_ODR_HIGH) +GPIO(EC_ENTERING_RW, PIN(E, 3), GPIO_OUT_LOW) +GPIO(EC_PROCHOT_ODL, PIN(6, 3), GPIO_ODR_HIGH) +GPIO(CPU_C10_GATE_L, PIN(6, 7), GPIO_INPUT) /* TODO - b/141322107 - implement if board power sequencing insufficient */ +GPIO(SYS_RST_ODL, PIN(C, 5), GPIO_ODR_HIGH) + +GPIO(EC_PCH_INT_ODL, PIN(D, 6), GPIO_ODR_HIGH) /* TODO - b/140557015 - implement with MKBD sensor events */ /* USB and USBC Signals */ @@ -59,3 +73,9 @@ ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0) /* UART */ ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0) /* UART from EC to Servo */ +/* Power Switch Logic (PSL) inputs */ +ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0) /* GPIOD2 = EC_LID_OPEN */ +ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0) /* GPIO00 = ACOK_OD, + GPIO01 = H1_EC_PWR_BTN_ODL + GPIO02 = EC_RST_ODL */ + |