diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2015-10-05 12:12:45 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-10-05 20:31:23 -0700 |
| commit | 217e72d700257057801ea6ba3620a368a89f9cbd (patch) | |
| tree | 6f7da957f4f344145a1c6d78b1faa5692f4511aa /chip/g/config_chip.h | |
| parent | 9e21514972c7d0b21e826e2edb2db7b8be2249ec (diff) | |
| download | chrome-ec-217e72d700257057801ea6ba3620a368a89f9cbd.tar.gz | |
cr50: upgrade to the latest FPGA image
This patch updates the EC codebase to match the suggested USB build
(20151005_041713). The spiflash utility must come from the same
tarball.
BRANCH=none
BUG=none
TEST=as follows:
- programmed the FPGA, it now reports the following when reset:
BootRom 0.8.91hw
- booted the new image using the latest spiflash version.
- disconnected the FPGA upgrade port, rebooted the device, entered
on the device console:
> spstp off
> spste
run on the workstation:
$ examples/spiraw.py -l 10 -f 800000
FT232H Future Technology Devices International, Ltd initialized at 857142 hertz
and observe on the DUT console:
Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11
>
Change-Id: Iff778087149ae3e7570f8fd4d81c2857a4ea5367
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/304123
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Diffstat (limited to 'chip/g/config_chip.h')
| -rw-r--r-- | chip/g/config_chip.h | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h index 8bef2e687a..50655d5e22 100644 --- a/chip/g/config_chip.h +++ b/chip/g/config_chip.h @@ -7,10 +7,7 @@ #define __CROS_EC_CONFIG_CHIP_H #include "core/cortex-m/config_core.h" - -/* Number of IRQ vectors on the NVIC */ -/* TODO_FPGA this should come from the generated .h file */ -#define CONFIG_IRQ_COUNT 192 +#include "cr50_fpga_regdefs.h" /* Describe the RAM layout */ #define CONFIG_RAM_BASE 0x10000 @@ -61,7 +58,9 @@ #define GPIO_PIN(port, index) GPIO_##port, (1 << index) #define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) -/* TODO_FPGA this should come from the generated .h file */ -#define PCLK_FREQ (24 * 1000 * 1000) +#define PCLK_FREQ (GC_CONST_FPGA_TIMER_FIXED_FREQ * 1000 * 1000) + +/* Number of IRQ vectors on the NVIC */ +#define CONFIG_IRQ_COUNT (GC_INTERRUPTS_COUNT - 16) #endif /* __CROS_EC_CONFIG_CHIP_H */ |