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| author | Hu, Hebo <hebo.hu@intel.com> | 2019-03-20 19:13:37 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-04-08 02:51:30 -0700 |
| commit | 014b6c86dfd1aa9ec9ffaba2647d4ca89baf1ef4 (patch) | |
| tree | 3038344894a47b863d96d266dc34a37884f0dfa1 /chip/ish/config_chip.h | |
| parent | 6a184d5019f0b45fe692da09a14e9ce7c853d68c (diff) | |
| download | chrome-ec-014b6c86dfd1aa9ec9ffaba2647d4ca89baf1ef4.tar.gz | |
ish/ish5: implement AON low power mode (D0i1-3)
1: D0i1(TCG) and D0i2(TCG + SRAM retention) implemented
2: D0i3 (TCG + SRAM power off) implemented
BUG=b:122364080
BRANCH=none
TEST=tested on arcada
Change-Id: I851d7c138b056a92d1616622e7cbfdfb94d86e5c
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1531772
Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Diffstat (limited to 'chip/ish/config_chip.h')
| -rw-r--r-- | chip/ish/config_chip.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h index 93cc527f6b..74432baca1 100644 --- a/chip/ish/config_chip.h +++ b/chip/ish/config_chip.h @@ -58,6 +58,10 @@ #define CONFIG_ISH_AON_SRAM_ROM_START (CONFIG_ISH_AON_SRAM_BASE_END - \ CONFIG_ISH_AON_SRAM_ROM_SIZE) +#define CONFIG_ISH_SRAM_BANK_SIZE 0x8000 +#define CONFIG_ISH_SRAM_BANKS (CONFIG_ISH_SRAM_SIZE / \ + CONFIG_ISH_SRAM_BANK_SIZE) + /* Required for panic_output */ #define CONFIG_RAM_SIZE CONFIG_ISH_SRAM_SIZE #define CONFIG_RAM_BASE CONFIG_ISH_SRAM_BASE_START |