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| author | Dino Li <Dino.Li@ite.com.tw> | 2018-07-18 17:42:21 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-07-20 15:10:14 -0700 |
| commit | 8a6674329235c0446aa1ce8b7ac36371c40308fe (patch) | |
| tree | 833f7d63183db1acdc84153ff724bbcc8d62fa52 /chip/it83xx/registers.h | |
| parent | ea1e1d667ae46556f86f072223030e9a57fe32cc (diff) | |
| download | chrome-ec-8a6674329235c0446aa1ce8b7ac36371c40308fe.tar.gz | |
IT8320DX: espi: reset espi module by FW
There is a bug on DX's espi_reset# pin.
So we can't enable hardware mechanism of espi_reset#.
To workaround this issue, this CL introduces a new macro to
config_chip.h IT83XX_ESPI_RESET_MODULE_BY_FW which is defined when
CHIP_VRAIANT is IT8320DX. When this macro is defined, the epsi hw
reset pin function is disabled. Instead, the interrupt handler for
this espi reset pin uses the GCTRL_RSTS register to force a reset of
VCC domain logic in the EC which resets the eSPI and LPC modules.
BUG=b:111480168
BRANCH=none
TEST=The eSPI module is reset when EC's espi_reset# pin is asserted.
Change-Id: Id7dfe746e7463c95735dde9a17777f3fce1030d0
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1138134
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index b91c18817e..227cdc2f99 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -538,6 +538,10 @@ #define IT83XX_GPIO_BASE 0x00F01600 #define IT83XX_GPIO_GCR REG8(IT83XX_GPIO_BASE+0x00) +#define IT83XX_GPIO_GCR_LPC_RST_B7 0x1 +#define IT83XX_GPIO_GCR_LPC_RST_D2 0x2 +#define IT83XX_GPIO_GCR_LPC_RST_DISABLE 0x3 +#define IT83XX_GPIO_GCR_LPC_RST_POS 1 #define IT83XX_GPIO_GPDRA REG8(IT83XX_GPIO_BASE+0x01) #define IT83XX_GPIO_GPDRB REG8(IT83XX_GPIO_BASE+0x02) |