ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 141 deletions

diff --git a/chip/max32660/clock_chip.c b/chip/max32660/clock_chip.c
deleted file mode 100644
index 901c5d559c..0000000000
--- a/chip/max32660/clock_chip.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Clocks and Power Management Module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-#include "tmr_regs.h"
-#include "gcr_regs.h"
-#include "pwrseq_regs.h"
-
-#define MAX32660_SYSTEMCLOCK SYS_CLOCK_HIRC
-
-/** Clock source */
-typedef enum {
-	SYS_CLOCK_NANORING = MXC_V_GCR_CLKCN_CLKSEL_NANORING, /**< 8KHz nanoring
-								 on MAX32660 */
-	SYS_CLOCK_HFXIN =
-		MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */
-	SYS_CLOCK_HFXIN_DIGITAL = 0x9,	/**< External Clock Input*/
-	SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC, /**< High Frequency
-							 Internal Oscillator */
-} sys_system_clock_t;
-
-/***** Functions ******/
-static void clock_wait_ready(uint32_t ready)
-{
-	// Start timeout, wait for ready
-	do {
-		if (MXC_GCR->clkcn & ready) {
-			return;
-		}
-	} while (1);
-}
-
-extern void (*const __isr_vector[])(void);
-uint32_t SystemCoreClock = HIRC96_FREQ;
-
-static void clock_update(void)
-{
-	uint32_t base_freq, divide, ovr;
-
-	// Get the clock source and frequency
-	ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
-	if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
-		base_freq = HIRC96_FREQ / 4;
-	} else {
-		if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
-			base_freq = HIRC96_FREQ / 2;
-		} else {
-			base_freq = HIRC96_FREQ;
-		}
-	}
-
-	// Get the clock divider
-	divide = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >>
-		 MXC_F_GCR_CLKCN_PSC_POS;
-
-	SystemCoreClock = base_freq >> divide;
-}
-
-void clock_init(void)
-{
-	/* Switch system clock to HIRC */
-	uint32_t ovr, divide;
-
-	// Set FWS higher than what the minimum for the fastest clock is
-	MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-			   (0x5UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-
-	// Enable 96MHz Clock
-	MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC_EN;
-
-	// Wait for the 96MHz clock
-	clock_wait_ready(MXC_F_GCR_CLKCN_HIRC_RDY);
-
-	// Set 96MHz clock as System Clock
-	MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL,
-		     MXC_S_GCR_CLKCN_CLKSEL_HIRC);
-
-	// Wait for system clock to be ready
-	clock_wait_ready(MXC_F_GCR_CLKCN_CKRDY);
-
-	// Update the system core clock
-	clock_update();
-
-	// Get the clock divider
-	divide = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >>
-		 MXC_F_GCR_CLKCN_PSC_POS;
-
-	// get ovr setting
-	ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
-
-	// Set flash wait settings
-	if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
-		if (divide == 0) {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		} else {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		}
-	} else if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
-		if (divide == 0) {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		} else {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		}
-	} else {
-		if (divide == 0) {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x4UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		} else if (divide == 1) {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		} else {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		}
-	}
-}