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| author | Jerry Bradshaw <jerry.bradshaw@maximintegrated.com> | 2019-10-16 12:36:00 -0500 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-11-02 04:07:08 +0000 |
| commit | 7d4547799ca33dbc8806f2d7db99ca58d26173c6 (patch) | |
| tree | a44a09062c2446670701578d11c9c9de689f1a6c /chip/max32660/i2c_regs.h | |
| parent | 4cb953efdb5413b3ad5a3853fa4e6c70b149901f (diff) | |
| download | chrome-ec-7d4547799ca33dbc8806f2d7db99ca58d26173c6.tar.gz | |
max32660: add I2C board address support, refactor
Adds support for a second I2C slave address, modeled on the same feature
in the STM32-F4. Also refactored the I2C slave interrupt handler to
streamline host read and writes, reduced I2C slave state variable usage,
and make better use of I2C slave interrupt types.
BRANCH=none
BUG=none
TEST=Slave tested with EC CMDs and board cmds sent from a custom written
EC HOST using another MAX32660 device as an I2C Master. Tested with
Raspberry PI that emulates EC HOST and board commands.
Change-Id: I575a283a9a6735b16f4b6ac0fcb0aa2d1984ee92
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1864791
Reviewed-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Tested-by: Harry Cutts <hcutts@chromium.org>
Commit-Queue: Sean Abraham <seanabraham@chromium.org>
Diffstat (limited to 'chip/max32660/i2c_regs.h')
| -rw-r--r-- | chip/max32660/i2c_regs.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/chip/max32660/i2c_regs.h b/chip/max32660/i2c_regs.h index e87de5d11d..8cd2fd8868 100644 --- a/chip/max32660/i2c_regs.h +++ b/chip/max32660/i2c_regs.h @@ -832,6 +832,23 @@ typedef struct { INT_FL0_TX_LOCK_OUT \ Mask */ +#define MXC_F_I2C_INT_FL0_MAMI_POS 16 /**< INT_FL0_MAMI Position */ +/* INT_FL0_MAMI Mask */ +#define MXC_F_I2C_INT_FL0_MAMI_MASK \ + ((uint32_t)(0xFUL << MXC_F_I2C_INT_FL0_MAMI_POS)) +/* INT_FL0_MAMI Address Match 0 */ +#define MXC_F_I2C_INT_FL0_MAMI_MATCH_0 \ + ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_MAMI_POS)) +/* INT_FL0_MAMI Address Match 1 */ +#define MXC_F_I2C_INT_FL0_MAMI_MATCH_1 \ + ((uint32_t)(0x2UL << MXC_F_I2C_INT_FL0_MAMI_POS)) +/* INT_FL0_MAMI Address Match 2 */ +#define MXC_F_I2C_INT_FL0_MAMI_MATCH_2 \ + ((uint32_t)(0x4UL << MXC_F_I2C_INT_FL0_MAMI_POS)) +/* INT_FL0_MAMI Address Match 3 */ +#define MXC_F_I2C_INT_FL0_MAMI_MATCH_3 \ + ((uint32_t)(0x8UL << MXC_F_I2C_INT_FL0_MAMI_POS)) + /** * Interrupt Enable Register. */ |