diff options
| author | Ricardo Quesada <ricardoq@google.com> | 2022-03-28 16:51:02 -0700 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-03-29 15:56:40 +0000 |
| commit | bfeb34faaad39675e65ef3a8c1c77ba0ddba879d (patch) | |
| tree | a8948fe3092183d91eedd7f51eb744dbb86c03d8 /chip/max32660/i2c_regs.h | |
| parent | d7ffcd69db110da6dbffc04c5c1671df6c8cc973 (diff) | |
| download | chrome-ec-bfeb34faaad39675e65ef3a8c1c77ba0ddba879d.tar.gz | |
COIL: update chip/max32660
This CL updates chip/max32660 according to the COIL guidelines.
This CL only updates "slave" with "target".
BRANCH=None
BUG=b:163885307
TEST=compare_build.sh -b max32660-eval matches
Change-Id: Ia2a2a9b8dca37cc190afda3f9281a77665191a2d
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3556503
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Ricardo Quesada <ricardoq@chromium.org>
Tested-by: Ricardo Quesada <ricardoq@chromium.org>
Auto-Submit: Ricardo Quesada <ricardoq@chromium.org>
Diffstat (limited to 'chip/max32660/i2c_regs.h')
| -rw-r--r-- | chip/max32660/i2c_regs.h | 85 |
1 files changed, 43 insertions, 42 deletions
diff --git a/chip/max32660/i2c_regs.h b/chip/max32660/i2c_regs.h index 3b59a2fb81..f6d2a6c0db 100644 --- a/chip/max32660/i2c_regs.h +++ b/chip/max32660/i2c_regs.h @@ -51,7 +51,7 @@ typedef struct { __IO uint32_t clk_hi; /* 0x38: I2C CLK_HI Register */ __IO uint32_t hs_clk; /* 0x3C: I2C HS_CLK Register */ __IO uint32_t timeout; /* 0x40: I2C TIMEOUT Register */ - __IO uint32_t slave_addr; /* 0x44: I2C SLAVE_ADDR Register */ + __IO uint32_t target_addr; /* 0x44: I2C TARGET_ADDR Register */ __IO uint32_t dma; /* 0x48: I2C DMA Register */ } mxc_i2c_regs_t; @@ -76,7 +76,7 @@ typedef struct { #define MXC_R_I2C_CLK_HI 0x00000038UL #define MXC_R_I2C_HS_CLK 0x0000003CUL #define MXC_R_I2C_TIMEOUT 0x00000040UL -#define MXC_R_I2C_SLAVE_ADDR 0x00000044UL +#define MXC_R_I2C_TARGET_ADDR 0x00000044UL #define MXC_R_I2C_DMA 0x00000048UL /** @@ -101,11 +101,11 @@ typedef struct { #define MXC_F_I2C_CTRL_MST_POS 1 /* CTRL_MST Mask */ #define MXC_F_I2C_CTRL_MST (0x1UL << MXC_F_I2C_CTRL_MST_POS) -/* CTRL_MST_SLAVE_MODE Value */ -#define MXC_V_I2C_CTRL_MST_SLAVE_MODE 0x0UL -/* CTRL_MST_SLAVE_MODE Setting */ -#define MXC_S_I2C_CTRL_MST_SLAVE_MODE \ - (MXC_V_I2C_CTRL_MST_SLAVE_MODE << MXC_F_I2C_CTRL_MST_POS) +/* CTRL_MST_TARGET_MODE Value */ +#define MXC_V_I2C_CTRL_MST_TARGET_MODE 0x0UL +/* CTRL_MST_TARGET_MODE Setting */ +#define MXC_S_I2C_CTRL_MST_TARGET_MODE \ + (MXC_V_I2C_CTRL_MST_TARGET_MODE << MXC_F_I2C_CTRL_MST_POS) /* CTRL_MST_CONTROLLER_MODE Value */ #define MXC_V_I2C_CTRL_MST_CONTROLLER_MODE 0x1UL /* CTRL_MST_CONTROLLER_MODE Setting */ @@ -1289,42 +1289,43 @@ typedef struct { #define MXC_F_I2C_TIMEOUT_TO (0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS) /** - * Slave Address Register. + * Target Address Register. */ -/* SLAVE_ADDR_SLAVE_ADDR Position */ -#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0 -/* SLAVE_ADDR_SLAVE_ADDR Mask */ -#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR \ - (0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS) - -/* SLAVE_ADDR_SLAVE_ADDR_DIS Position */ -#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS 10 -/* SLAVE_ADDR_SLAVE_ADDR_DIS Mask */ -#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS \ - (0x1UL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS) - -/* SLAVE_ADDR_SLAVE_ADDR_IDX Position */ -#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS 11 -/* SLAVE_ADDR_SLAVE_ADDR_IDX Mask */ -#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX \ - (0xFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS) - -/* SLAVE_ADDR_EX_ADDR Position */ -#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15 -/* SLAVE_ADDR_EX_ADDR Mask */ -#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR (0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) -/* SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Value */ -#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS 0x0UL -/* SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Setting */ -#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \ - (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \ - << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) -/* SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Value */ -#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS 0x1UL -/* SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Setting */ -#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \ - (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \ - << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) +/* TARGET_ADDR_TARGET_ADDR Position */ +#define MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_POS 0 +/* TARGET_ADDR_TARGET_ADDR Mask */ +#define MXC_F_I2C_TARGET_ADDR_TARGET_ADDR \ + (0x3FFUL << MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_POS) + +/* TARGET_ADDR_TARGET_ADDR_DIS Position */ +#define MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_DIS_POS 10 +/* TARGET_ADDR_TARGET_ADDR_DIS Mask */ +#define MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_DIS \ + (0x1UL << MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_DIS_POS) + +/* TARGET_ADDR_TARGET_ADDR_IDX Position */ +#define MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_IDX_POS 11 +/* TARGET_ADDR_TARGET_ADDR_IDX Mask */ +#define MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_IDX \ + (0xFUL << MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_IDX_POS) + +/* TARGET_ADDR_EX_ADDR Position */ +#define MXC_F_I2C_TARGET_ADDR_EX_ADDR_POS 15 +/* TARGET_ADDR_EX_ADDR Mask */ +#define MXC_F_I2C_TARGET_ADDR_EX_ADDR \ + (0x1UL << MXC_F_I2C_TARGET_ADDR_EX_ADDR_POS) +/* TARGET_ADDR_EX_ADDR_7_BITS_ADDRESS Value */ +#define MXC_V_I2C_TARGET_ADDR_EX_ADDR_7_BITS_ADDRESS 0x0UL +/* TARGET_ADDR_EX_ADDR_7_BITS_ADDRESS Setting */ +#define MXC_S_I2C_TARGET_ADDR_EX_ADDR_7_BITS_ADDRESS \ + (MXC_V_I2C_TARGET_ADDR_EX_ADDR_7_BITS_ADDRESS \ + << MXC_F_I2C_TARGET_ADDR_EX_ADDR_POS) +/* TARGET_ADDR_EX_ADDR_10_BITS_ADDRESS Value */ +#define MXC_V_I2C_TARGET_ADDR_EX_ADDR_10_BITS_ADDRESS 0x1UL +/* TARGET_ADDR_EX_ADDR_10_BITS_ADDRESS Setting */ +#define MXC_S_I2C_TARGET_ADDR_EX_ADDR_10_BITS_ADDRESS \ + (MXC_V_I2C_TARGET_ADDR_EX_ADDR_10_BITS_ADDRESS \ + << MXC_F_I2C_TARGET_ADDR_EX_ADDR_POS) /** * DMA Register. |