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authorJack Rosenthal <jrosenth@chromium.org>2021-11-04 12:11:58 -0600
committerCommit Bot <commit-bot@chromium.org>2021-11-05 04:22:34 +0000
commit252457d4b21f46889eebad61d4c0a65331919cec (patch)
tree01856c4d31d710b20e85a74c8d7b5836e35c3b98 /chip/mchp/qmspi_chip.h
parent08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff)
downloadchrome-ec-stabilize-quickfix-14695.124.B-ish.tar.gz
In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'chip/mchp/qmspi_chip.h')
-rw-r--r--chip/mchp/qmspi_chip.h67
1 files changed, 0 insertions, 67 deletions
diff --git a/chip/mchp/qmspi_chip.h b/chip/mchp/qmspi_chip.h
deleted file mode 100644
index 1a1d764267..0000000000
--- a/chip/mchp/qmspi_chip.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for MEC17xx processor
- */
-/** @file qmspi_chip.h
- *MEC17xx Quad SPI Master
- */
-/** @defgroup MCHP MEC qmspi
- */
-
-#ifndef _QMSPI_CHIP_H
-#define _QMSPI_CHIP_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-/* struct spi_device_t */
-#include "spi.h"
-
-
-int qmspi_transaction_flush(const struct spi_device_t *spi_device);
-
-int qmspi_transaction_wait(const struct spi_device_t *spi_device);
-
-int qmspi_transaction_sync(const struct spi_device_t *spi_device,
- const uint8_t *txdata, int txlen,
- uint8_t *rxdata, int rxlen);
-
-int qmspi_transaction_async(const struct spi_device_t *spi_device,
- const uint8_t *txdata, int txlen,
- uint8_t *rxdata, int rxlen);
-
-int qmspi_enable(int port, int enable);
-
-/*
- * QMSPI0 Start
- * flags
- * b[0] = ignored
- * b[1] = 1 enable QMSPI interrupts
- * b[2] = 1 start
- */
-void qmspi_cfg_irq_start(uint8_t flags);
-
-/*
- * QMSPI transmit and/or receive
- * np_flags
- * b[7:0] = flags
- * b[0] = close(de-assert chip select when done)
- * b[1] = enable Done and ProgError interrupt
- * b[2] = start
- * b[15:8] = number of tx pins
- * b[24:16] = number of rx pins
- *
- * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR
- * or error (bit[7]==1)
- */
-uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
- uint32_t np_flags,
- const uint8_t *txdata, uint32_t ntx,
- uint8_t *rxdata, uint32_t nrx);
-
-#endif /* #ifndef _QMSPI_CHIP_H */
-/** @}
- */
-